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| User's Manual PD789426, 789436, 789446 789456 Subseries 8-Bit Single-Chip Microcontrollers PD789425 PD789426 PD789435 PD789436 PD78F9436 PD789445 PD789446 PD789455 PD789456 PD78F9456 Document No. U15075EJ1V0UM00 (1st edition) Date Published November 2000 N CP(K) 1999 2000 (c) Printed in Japan [MEMO] 2 User's Manual U15075EJ1V0UM00 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. OSF/Motif is a trademark of Open Software Foundation, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. User's Manual U15075EJ1V0UM00 3 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD78F9436, 78F9456 The customer must judge the need for license: PD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 * The information in this document is current as of September, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00.4 4 User's Manual U15075EJ1V0UM00 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 User's Manual U15075EJ1V0UM00 5 [MEMO] 6 User's Manual U15075EJ1V0UM00 INTRODUCTION Target Readers This manual is intended to give user engineers an understanding of the functions of the PD789426, 789436, 789446, and 789456 Subseries to design and develop its application systems and programs. Target products: * PD789426 Subseries: * PD789436 Subseries: * PD789446 Subseries: * PD789456 Subseries: PD789425, 789426 PD789435, 789436 PD789445, 789446 PD789455, 789456 Purpose This manual is designed to deepen your understanding of the following functions using the following organization. Organization Two manuals are available for the PD789426, 789436, 789446, and 789456 Subseries: This manual and the instruction manual (common to the 78K/0S Series). PD789426, 789436, 789446, and 789456 Subseries User's Manual * Pin functions * Internal block functions * Interrupts * Other internal peripheral functions How to Use This Manual 78K/0S Series User's Manual Instructions * CPU function * Instruction set * Instruction description It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * To understand the overall functions of the PD789426, 789436, 789446, and 789456 Subseries Read this manual in the order of the CONTENTS. * How to read register formats The name of a bit whose number is enclosed in brackets is reserved for the assembler and is defined for the C compiler by the header file sfrbit.h. * To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX. * To learn the details of the instruction functions of the 78K/0S series Refer to 78K/0S Series Instructions User's Manual (U11047E) separately available. User's Manual U15075EJ1V0UM00 7 Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document No. Document Name Japanese English U14493E PD789425, 789426, 789435, 789436, 789445, 789446, 789455, 789456 Preliminary Product Information PD78F9436, 78F9456 Preliminary Product Information PD789426, 789436, 789446, 789456 Subseries User's Manual 78K/0S Series Instructions User's Manual 78K/0, 78K/0S Series Flash Memory Write Application Note U14493J To be prepared U15075J U11047J U14458J To be prepared This manual U11047E U14458E Documents Related to Development Tools (User's Manuals) Document No. Document Name Japanese RA78K0S Assembler Package Operation Assembly Language Structured Assembly Language CC78K/0S C Compiler Operation Language SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later TM Windows Based SM78K Series System Simulator Operation U11622J U11599J U11623J English U11622E U11599E U11623E U11816J U11817J U14611J U11816E U11817E To be prepared External Part User Open Interface Specifications Reference Operation U10092J U10092E ID78K0S-NS Integrated Debugger Windows Based ID78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Based IE-78K0S-NS IE-789456-NS-EM1 U12901J U14910J U12901E To be prepared U13549J To be prepared U13549E To be prepared Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 8 User's Manual U15075EJ1V0UM00 Document Related to Embedded Software (User's Manual) Document No. Document Name Japanese 78K/0S Series OS MX78K0S Fundamental U12938J English U12938E Other Related Documents Document No. Document Name Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Parties X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E -- English Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U15075EJ1V0UM00 9 [MEMO] 10 User's Manual U15075EJ1V0UM00 CONTENTS CHAPTER 1 GENERAL ...........................................................................................................................25 1.1 1.2 1.3 1.4 Features.......................................................................................................................................25 Applications ................................................................................................................................25 Ordering Information .................................................................................................................26 Pin Configuration (Top View) ....................................................................................................27 1.4.1 1.4.2 Pin configuration of PD789426, 789436 Subseries (Top View) ................................................. 27 Pin configuration of PD789446, 789456 Subseries (Top View) ................................................. 28 1.5 1.6 78K/0S Series Lineup .................................................................................................................30 Block Diagram ............................................................................................................................32 1.6.1 1.6.2 Block diagram of PD789426, 789436 Subseries........................................................................ 32 Block diagram of PD789446, 789456 Subseries........................................................................ 33 1.7 Overview of Functions...............................................................................................................34 CHAPTER 2 PIN FUNCTIONS................................................................................................................37 2.1 2.2 List of Pin Functions..................................................................................................................37 Description of Pin Functions ....................................................................................................40 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 P00 to P03 (Port 0)....................................................................................................................... 40 P10, P11 (Port 1).......................................................................................................................... 40 P20 to P26 (Port 2)....................................................................................................................... 40 P30 to P33 (Port 3)....................................................................................................................... 41 P50 to P53 (Port 5)....................................................................................................................... 41 P60 to P65 (Port 6)....................................................................................................................... 41 P70 to P72 (Port 7)....................................................................................................................... 42 P80, P81 (Port 8).......................................................................................................................... 42 P90 to P97 (Port 9)....................................................................................................................... 42 S0 to S14...................................................................................................................................... 42 COM0 to COM3 ............................................................................................................................ 42 VLC0 to VLC2 ................................................................................................................................... 42 CAPH, CAPL ................................................................................................................................ 42 RESET.......................................................................................................................................... 42 X1, X2........................................................................................................................................... 42 XT1, XT2 ...................................................................................................................................... 42 VDD................................................................................................................................................ 43 VSS ................................................................................................................................................ 43 VPP (PD78F9436, 78F9456 only)................................................................................................ 43 IC (mask ROM version only)......................................................................................................... 43 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ........................44 CHAPTER 3 CPU ARCHITECTURE.......................................................................................................47 3.1 Memory Space ............................................................................................................................47 3.1.1 Internal program memory space................................................................................................... 53 User's Manual U15075EJ1V0UM00 11 3.1.2 3.1.3 3.1.4 Internal data memory (internal high-speed RAM) space .............................................................. 54 Special function register (SFR) area............................................................................................. 54 Data memory addressing.............................................................................................................. 55 Control registers ........................................................................................................................... 61 General-purpose registers ............................................................................................................ 64 Special function registers (SFRs) ................................................................................................. 65 Relative addressing ...................................................................................................................... 68 Immediate addressing .................................................................................................................. 69 Table indirect addressing ............................................................................................................. 70 Register addressing...................................................................................................................... 70 Direct addressing.......................................................................................................................... 71 Short direct addressing................................................................................................................. 72 Special function register (SFR) addressing .................................................................................. 73 Register addressing...................................................................................................................... 74 Register indirect addressing ......................................................................................................... 75 Based addressing ......................................................................................................................... 76 Stack addressing .......................................................................................................................... 76 3.2 Processor Registers.................................................................................................................. 61 3.2.1 3.2.2 3.2.3 3.3 Instruction Address Addressing.............................................................................................. 68 3.3.1 3.3.2 3.3.3 3.3.4 3.4 Operand Address Addressing.................................................................................................. 71 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 77 4.1 4.2 Port Functions ........................................................................................................................... 77 Port Configuration..................................................................................................................... 80 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 Port 0 ............................................................................................................................................ 81 Port 1 ............................................................................................................................................ 82 Port 2 ............................................................................................................................................ 83 Port 3 ............................................................................................................................................ 89 Port 5 ............................................................................................................................................ 91 Port 6 ............................................................................................................................................ 92 Port 7 ............................................................................................................................................ 93 Port 8 (PD789426, 789436 Subseries only) ............................................................................... 94 Port 9 (PD789426, 789436 Subseries only) ............................................................................... 95 4.3 4.4 Registers Controlling Port Function........................................................................................ 96 Port Function Operation ......................................................................................................... 102 4.4.1 4.4.2 4.4.3 Writing to I/O port........................................................................................................................ 102 Reading from I/O port ................................................................................................................. 102 Arithmetic operation of I/O port................................................................................................... 102 CHAPTER 5 CLOCK GENERATOR.................................................................................................... 103 5.1 5.2 5.3 5.4 Clock Generator Functions .................................................................................................... 103 Clock Generator Configuration .............................................................................................. 103 Registers Controlling Clock Generator ................................................................................. 105 System Clock Oscillators ....................................................................................................... 108 5.4.1 Main system clock oscillator ....................................................................................................... 108 User's Manual U15075EJ1V0UM00 12 5.4.2 5.4.3 5.4.4 Subsystem clock oscillator ......................................................................................................... 109 Divider circuit .............................................................................................................................. 111 When no subsystem clock is used ............................................................................................. 111 5.5 5.6 Clock Generator Operation .....................................................................................................112 Changing Setting of System Clock and CPU Clock..............................................................113 5.6.1 5.6.2 Time required for switching between system clock and CPU clock ........................................... 113 Switching between system clock and CPU clock ....................................................................... 114 CHAPTER 6 16-BIT TIMER ..................................................................................................................115 6.1 6.2 6.3 6.4 16-Bit Timer Functions ............................................................................................................115 16-Bit Timer Configuration ......................................................................................................116 Registers Controlling 16-Bit Timer .........................................................................................119 16-Bit Timer Operation.............................................................................................................123 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 Operation as timer interrupt........................................................................................................ 123 Operation as timer output ........................................................................................................... 125 Capture operation....................................................................................................................... 126 16-bit timer counter 90 readout .................................................................................................. 127 Buzzer output operation ............................................................................................................. 128 6.5 Notes on Using 16-Bit Timer ...................................................................................................129 CHAPTER 7 8-BIT TIMER ....................................................................................................................131 7.1 7.2 7.3 7.4 8-Bit Timer Functions ..............................................................................................................131 8-Bit Timer Configuration ........................................................................................................132 Registers Controlling 8-Bit Timer ...........................................................................................138 8-Bit Timer Operation...............................................................................................................143 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 Operation as 8-bit timer counter ................................................................................................. 143 Operation as 16-bit timer counter ............................................................................................... 153 Operation as carrier generator ................................................................................................... 160 PWM free-running mode operation (timer 50) ............................................................................ 164 Operation as PWM output (timer 60) .......................................................................................... 168 7.5 Notes on Using 8-Bit Timer .....................................................................................................170 CHAPTER 8 WATCH TIMER ................................................................................................................171 8.1 8.2 8.3 8.4 Watch Timer Functions............................................................................................................171 Watch Timer Configuration .....................................................................................................172 Watch Timer Control Register.................................................................................................173 Watch Timer Operation ............................................................................................................174 8.4.1 8.4.2 Operation as watch timer............................................................................................................ 174 Operation as interval timer ......................................................................................................... 174 CHAPTER 9 WATCHDOG TIMER........................................................................................................177 9.1 9.2 9.3 Watchdog Timer Functions .....................................................................................................177 Watchdog Timer Configuration...............................................................................................178 Watchdog Timer Control Registers ........................................................................................179 13 User's Manual U15075EJ1V0UM00 9.4 Watchdog Timer Operation .................................................................................................... 181 9.4.1 9.4.2 Operation as watchdog timer...................................................................................................... 181 Operation as interval timer.......................................................................................................... 182 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES)........................ 183 10.1 10.2 10.3 10.4 8-Bit A/D Converter Functions ............................................................................................... 183 8-Bit A/D Converter Configuration......................................................................................... 183 8-Bit A/D Converter Control Registers .................................................................................. 186 8-Bit A/D Converter Operation ............................................................................................... 188 10.4.1 10.4.2 10.4.3 Basic operation of 8-bit A/D converter ........................................................................................ 188 Input voltage and conversion result............................................................................................ 189 Operation mode of 8-bit A/D converter ....................................................................................... 191 10.5 Cautions Related to 8-Bit A/D Converter............................................................................... 192 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES)...................... 197 11.1 11.2 11.3 11.4 10-Bit A/D Converter Functions ............................................................................................. 197 10-Bit A/D Converter Configuration....................................................................................... 197 10-Bit A/D Converter Control Registers ................................................................................ 200 10-Bit A/D Converter Operation ............................................................................................. 202 11.4.1 11.4.2 11.4.3 Basic operation of 10-bit A/D converter ...................................................................................... 202 Input voltage and conversion result............................................................................................ 203 Operation mode of 10-bit A/D converter ..................................................................................... 205 11.5 Cautions Related to 10-Bit A/D Converter............................................................................. 206 CHAPTER 12 SERIAL INTERFACE 20 .............................................................................................. 211 12.1 12.2 12.3 12.4 Serial Interface 20 Functions.................................................................................................. 211 Serial Interface 20 Configuration ........................................................................................... 211 Serial Interface 20 Control Registers..................................................................................... 215 Serial Interface 20 Operation .................................................................................................. 222 12.4.1 12.4.2 12.4.3 Operation stop mode .................................................................................................................. 222 Asynchronous serial interface (UART) mode ............................................................................. 224 3-wire serial I/O mode................................................................................................................. 237 CHAPTER 13 LCD CONTROLLER/DRIVER....................................................................................... 247 13.1 13.2 13.3 13.4 13.5 13.6 13.7 LCD Controller/Driver Functions ........................................................................................... 247 LCD Controller/Driver Configuration ..................................................................................... 247 Registers Controlling LCD Controller/Driver ........................................................................ 249 Setting LCD Controller/Driver ................................................................................................ 253 LCD Display Data Memory...................................................................................................... 253 Common and Segment Signals.............................................................................................. 254 Display Modes.......................................................................................................................... 256 13.7.1 13.7.2 Three-time slot display example ................................................................................................. 256 Four-time slot display example ................................................................................................... 259 14 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS.............................................................................................263 14.1 14.2 14.3 14.4 Interrupt Function Types .........................................................................................................263 Interrupt Sources and Configuration .....................................................................................263 Registers Controlling Interrupt Function...............................................................................266 Interrupt Servicing Operation .................................................................................................272 14.4.1 14.4.2 14.4.3 14.4.4 Non-maskable interrupt request acknowledgment operation ..................................................... 272 Maskable interrupt request acknowledgment operation ............................................................. 274 Multiple interrupt servicing.......................................................................................................... 275 Putting interrupt requests on hold............................................................................................... 277 CHAPTER 15 STANDBY FUNCTION ..................................................................................................279 15.1 Standby Function and Configuration .....................................................................................279 15.1.1 15.1.2 15.2.1 15.2.2 Standby function......................................................................................................................... 279 Register controlling standby function.......................................................................................... 280 HALT mode ................................................................................................................................ 281 STOP mode ................................................................................................................................ 284 15.2 Standby Function Operation ...................................................................................................281 CHAPTER 16 RESET FUNCTION ........................................................................................................287 CHAPTER 17 PD78F9436, 78F9456 ...................................................................................................291 17.1 Flash Memory Programming ...................................................................................................292 17.1.1 17.1.2 17.1.3 17.1.4 Selecting communication mode.................................................................................................. 292 Function of flash memory programming ..................................................................................... 293 Flashpro III connection example................................................................................................. 293 Example of settings for Flashpro III (PG-FP3)............................................................................ 295 CHAPTER 18 MASK OPTIONS............................................................................................................297 CHAPTER 19 INSTRUCTION SET .......................................................................................................299 19.1 Operation...................................................................................................................................299 19.1.1 19.1.2 19.1.3 Operand identifiers and description methods ............................................................................. 299 Description of "Operation" column.............................................................................................. 300 Description of "Flag" column....................................................................................................... 300 19.2 Operation List ...........................................................................................................................301 19.3 Instructions Listed by Addressing Type................................................................................306 APPENDIX A DEVELOPMENT TOOLS ...............................................................................................309 A.1 A.2 A.3 Language Processing Software..............................................................................................311 Flash Memory Writing Tools ...................................................................................................312 Debugging Tools ......................................................................................................................313 A.3.1 A.3.2 Hardware .................................................................................................................................... 313 Software ..................................................................................................................................... 314 User's Manual U15075EJ1V0UM00 15 APPENDIX B EMBEDDED SOFTWARE ............................................................................................. 315 APPENDIX C REGISTER INDEX......................................................................................................... 317 C.1 C.2 Register Index (Alphabetic Order of Register Name) .......................................................... 317 Register Index (Alphabetic Order of Register Symbol) ....................................................... 319 16 User's Manual U15075EJ1V0UM00 LIST OF FIGURES (1/5) Figure No. 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 Title Page Pin Input/Output Circuits ............................................................................................................................... 45 Memory Map (PD789425, 789435) ............................................................................................................. 47 Memory Map (PD789426, 789436) ............................................................................................................. 48 Memory Map (PD78F9436)......................................................................................................................... 49 Memory Map (PD789445, 789455) ............................................................................................................. 50 Memory Map (PD789446, 789456) ............................................................................................................. 51 Memory Map (PD78F9456)......................................................................................................................... 52 Data Memory Addressing (PD789425, 789435) ......................................................................................... 55 Data Memory Addressing (PD789426, 789436) ......................................................................................... 56 Data Memory Addressing (PD78F9436) ..................................................................................................... 57 Data Memory Addressing (PD789445, 789455) ......................................................................................... 58 Data Memory Addressing (PD789446, 789456) ......................................................................................... 59 Data Memory Addressing (PD78F9456) ..................................................................................................... 60 Program Counter Configuration .................................................................................................................... 61 Program Status Word Configuration ............................................................................................................. 61 Stack Pointer Configuration .......................................................................................................................... 63 Data to Be Saved to Stack Memory .............................................................................................................. 63 Data to Be Restored from Stack Memory...................................................................................................... 63 General-Purpose Register Configuration ...................................................................................................... 64 Port Types (PD789426, 789436 Subseries) ............................................................................................... 77 Port Types (PD789446, 789456 Subseries) ............................................................................................... 78 Block Diagram of P00 to P03 ........................................................................................................................ 81 Block Diagram of P10 and P11 ..................................................................................................................... 82 Block Diagram of P20.................................................................................................................................... 83 Block Diagram of P21 and P26 ..................................................................................................................... 84 Block Diagram of P22.................................................................................................................................... 85 Block Diagram of P23.................................................................................................................................... 86 Block Diagram of P24.................................................................................................................................... 87 Block Diagram of P25.................................................................................................................................... 88 Block Diagram of P30.................................................................................................................................... 89 Block Diagram of P31 to P33 ........................................................................................................................ 90 Block Diagram of P50 to P53 ........................................................................................................................ 91 Block Diagram of Port 6 ................................................................................................................................ 92 Block Diagram of P70 to P72 ........................................................................................................................ 93 Block Diagram of P80, P81 ........................................................................................................................... 94 Block Diagram of P90 to P97 ........................................................................................................................ 95 Format of Port Mode Register ....................................................................................................................... 97 Format of Pull-Up Resistor Option Register 0 ............................................................................................... 98 Format of Pull-Up Resistor Option Register B2............................................................................................. 99 Format of Pull-Up Resistor Option Register B3............................................................................................. 99 User's Manual U15075EJ1V0UM00 17 LIST OF FIGURES (2/5) Figure No. 4-22 4-23 4-24 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 Title Page Format of Pull-Up Resistor Option Register B7........................................................................................... 100 Format of Pull-Up Resistor Option Register B8........................................................................................... 100 Format of Pull-Up Resistor Option Register B9........................................................................................... 101 Block Diagram of Clock Generator .............................................................................................................. 104 Format of Processor Clock Control Register ............................................................................................... 105 Format of Suboscillation Mode Register ..................................................................................................... 106 Format of Subclock Control Register .......................................................................................................... 107 External Circuit of Main System Clock Oscillator ........................................................................................ 108 External Circuit of Subsystem Clock Oscillator ........................................................................................... 109 Examples of Incorrect Resonator Connection............................................................................................. 110 Switching Between System Clock and CPU Clock...................................................................................... 114 Block Diagram of 16-Bit Timer..................................................................................................................... 117 Format of 16-Bit Timer Mode Control Register 90....................................................................................... 120 Format of Buzzer Output Control Register 90 ............................................................................................. 121 Format of Port Mode Register 2 .................................................................................................................. 122 Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation ...................................... 123 Timing of Timer Interrupt Operation ............................................................................................................ 124 Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation ......................................... 125 Timer Output Timing.................................................................................................................................... 125 Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation ................................................. 126 Capture Operation Timing (Both Edges of CPT90 Pin Are Specified) ........................................................ 126 16-Bit Timer Counter 90 Readout Timing.................................................................................................... 127 Settings of Buzzer Output Control Register 90 for Buzzer Output Operation.............................................. 128 Block Diagram of Timer 50 .......................................................................................................................... 133 Block Diagram of Timer 60 .......................................................................................................................... 134 Block Diagram of Output Controller (Timer 60) ........................................................................................... 135 Format of 8-Bit Timer Mode Control Register 50......................................................................................... 139 Format of 8-Bit Timer Mode Control Register 60......................................................................................... 141 Format of Carrier Generator Output Control Register 60 ............................................................................ 142 Format of Port Mode Register 3 .................................................................................................................. 142 Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) ............................................... 145 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H) ............................... 145 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) ............................... 146 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) ..... 146 Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) ..... 147 Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is Selected for Timer 50 Count Clock) ............................................................................................................ 148 Timing of Operation of External Event Counter with 8-Bit Resolution ........................................................ 150 Timing of Square-Wave Output with 8-Bit Resolution ................................................................................. 152 User's Manual U15075EJ1V0UM00 18 LIST OF FIGURES (3/5) Figure No. 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 8-1 8-2 8-3 9-1 9-2 9-3 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 11-1 11-2 11-3 11-4 Title Page Timing of Interval Timer Operation with 16-Bit Resolution .......................................................................... 155 Timing of External Event Counter Operation with 16-Bit Resolution........................................................... 157 Timing of Square-Wave Output with 16-Bit Resolution ............................................................................... 159 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N)) ........................................ 161 Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N), Phases of Carrier Clock and NRZ60 Are Asynchronous) ........................................................................... 162 Timing of Carrier Generator Operation (When CR60 = CRH60 = N) .......................................................... 163 Operation Timing in PWM Free-Running Mode (When Rising Edge Is Selected) ...................................... 165 Operation Timing When Overwriting CR50 (When Rising Edge Is Selected) ............................................. 165 Operation Timing in PWM Free-Running Mode (When Both Edges Are Selected) .................................... 166 Operation Timing in PWM Free-Running Mode (When Both Edges Are Selected) (When CR50 Is Overwritten) ....................................................................................................................... 167 PWM Pulse Generator Mode Timing (Basic Operation).............................................................................. 169 PWM Output Mode Timing (When CR60 and CRH60 Are Overwritten)...................................................... 169 Start Timing of 8-Bit Timer Counter............................................................................................................. 170 Timing of Operation as External Event Counter (8-Bit Resolution) ............................................................. 170 Block Diagram of Watch Timer.................................................................................................................... 171 Format of Watch Timer Mode Control Register........................................................................................... 173 Watch Timer/Interval Timer Operation Timing ............................................................................................ 175 Block Diagram of Watchdog Timer.............................................................................................................. 178 Format of Watchdog Timer Clock Select Register ...................................................................................... 179 Format of Watchdog Timer Mode Register ................................................................................................. 180 Block Diagram of 8-Bit A/D Converter......................................................................................................... 184 Format of A/D Converter Mode Register 0.................................................................................................. 186 Format of Analog Input Channel Specification Register 0........................................................................... 187 Basic Operation of 8-Bit A/D Converter....................................................................................................... 189 Relationship Between Analog Input Voltage and A/D Conversion Result................................................... 190 Software-Started A/D Conversion ............................................................................................................... 191 How to Reduce Current Consumption in Standby Mode............................................................................. 192 Conversion Result Read Timing (If Conversion Result Is Undefined)......................................................... 193 Conversion Result Read Timing (If Conversion Result Is Normal) ............................................................. 193 Analog Input Pin Treatment......................................................................................................................... 194 A/D Conversion End Interrupt Request Generation Timing ........................................................................ 195 AVDD Pin Handling....................................................................................................................................... 195 Block Diagram of 10-Bit A/D Converter....................................................................................................... 198 Format of A/D Converter Mode Register 0.................................................................................................. 200 Format of Analog Input Channel Specification Register 0........................................................................... 201 Basic Operation of 10-Bit A/D Converter..................................................................................................... 203 User's Manual U15075EJ1V0UM00 19 LIST OF FIGURES (4/5) Figure No. 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 14-1 14-2 14-3 14-4 14-5 14-6 Title Page Relationship Between Analog Input Voltage and A/D Conversion Result ................................................... 204 Software-Started A/D Conversion ............................................................................................................... 205 How to Reduce Current Consumption in Standby Mode............................................................................. 206 Conversion Result Read Timing (If Conversion Result Is Undefined)......................................................... 207 Conversion Result Read Timing (If Conversion Result Is Normal).............................................................. 207 Analog Input Pin Treatment......................................................................................................................... 208 A/D Conversion End Interrupt Request Generation Timing......................................................................... 209 AVDD Pin Handling....................................................................................................................................... 209 Block Diagram of Serial Interface 20........................................................................................................... 212 Block Diagram of Baud Rate Generator 20 ................................................................................................. 213 Format of Serial Operation Mode Register 20............................................................................................. 215 Format of Asynchronous Serial Interface Mode Register 20....................................................................... 216 Format of Asynchronous Serial Interface Status Register 20 ..................................................................... 218 Format of Baud Rate Generator Control Register 20 .................................................................................. 219 Format of Asynchronous Serial Interface Transmit/Receive Data............................................................... 231 Asynchronous Serial Interface Transmission Completion Interrupt Timing................................................. 233 Asynchronous Serial Interface Reception Completion Interrupt Timing ...................................................... 234 Receive Error Timing................................................................................................................................... 235 3-Wire Serial I/O Mode Timing .................................................................................................................... 240 Block Diagram of LCD Controller/Driver...................................................................................................... 248 Format of LCD Display Mode Register 0..................................................................................................... 250 Format of LCD Clock Control Register 0 ..................................................................................................... 251 Format of LCD Voltage Amplification Control Register 0 ............................................................................ 252 Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs (PD789446, 789456 Subseries) ................................................................................................................ 253 Common Signal Waveforms........................................................................................................................ 255 Voltages and Phases of Common and Segment Signals............................................................................ 255 Three-Time Slot LCD Display Pattern and Electrode Connections ............................................................. 256 Example of Connecting Three-Time Slot LCD Panel .................................................................................. 257 Three-Time Slot LCD Drive Waveform Examples ....................................................................................... 258 Four-Time Slot LCD Display Pattern and Electrode Connections ............................................................... 259 Example of Connecting Four-Time Slot LCD Panel .................................................................................... 260 Four-Time Slot LCD Drive Waveform Examples ......................................................................................... 261 Basic Configuration of Interrupt Function .................................................................................................... 265 Format of Interrupt Request Flag Registers ................................................................................................ 267 Format of Interrupt Mask Flag Registers ..................................................................................................... 268 Format of External Interrupt Mode Register 0 ............................................................................................. 269 Format of External Interrupt Mode Register 1 ............................................................................................. 270 Configuration of Program Status Word........................................................................................................ 270 User's Manual U15075EJ1V0UM00 20 LIST OF FIGURES (5/5) Figure No. 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 15-1 15-2 15-3 15-4 15-5 16-1 16-2 16-3 16-4 17-1 17-2 17-3 A-1 Title Page Format of Key Return Mode Register 00..................................................................................................... 271 Block Diagram of Falling Edge Detector ..................................................................................................... 271 Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment......................................... 273 Timing of Non-Maskable Interrupt Request Acknowledgment .................................................................... 273 Non-Maskable Interrupt Request Acknowledgment .................................................................................... 273 Interrupt Request Acknowledgment Program Algorithm ............................................................................. 274 Interrupt Request Acknowledgment Timing (Example: MOV A, r) .............................................................. 275 Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final Clock Under Execution) ................................................................................................ 275 Example of Multiple Interrupts..................................................................................................................... 276 Format of Oscillation Stabilization Time Select Register............................................................................. 280 Releasing HALT Mode by Interrupt ............................................................................................................. 282 Releasing HALT Mode by RESET Input ..................................................................................................... 283 Releasing STOP Mode by Interrupt ............................................................................................................ 285 Releasing STOP Mode by RESET Input..................................................................................................... 286 Block Diagram of Reset Function................................................................................................................ 287 Reset Timing by RESET Input .................................................................................................................... 288 Reset Timing by Overflow in Watchdog Timer ............................................................................................ 288 Reset Timing by RESET Input in STOP Mode ............................................................................................ 288 Communication Mode Selection Format ..................................................................................................... 292 Flashpro III Connection Example in 3-Wire Serial I/O Mode....................................................................... 293 Flashpro III Connection Example in UART Mode........................................................................................ 294 Development Tools ..................................................................................................................................... 310 User's Manual U15075EJ1V0UM00 21 LIST OF TABLES (1/2) Table No. 2-1 3-1 3-2 3-3 3-4 4-1 4-2 4-3 5-1 5-2 6-1 6-2 6-3 6-4 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 10-1 11-1 Title Page Types of Pin Input/Output Circuits................................................................................................................. 44 Internal ROM Capacity .................................................................................................................................. 53 Vector Table .................................................................................................................................................. 53 LCD Display RAM Capacity........................................................................................................................... 54 Special Function Register List....................................................................................................................... 66 Port Functions ............................................................................................................................................... 79 Configuration of Port ..................................................................................................................................... 80 Port Mode Register and Output Latch Settings When Using Alternate Functions ........................................ 98 Configuration of Clock Generator................................................................................................................ 103 Maximum Time Required for Switching CPU Clock .................................................................................... 113 16-Bit Timer Configuration .......................................................................................................................... 116 Interval Time of 16-Bit Timer ....................................................................................................................... 123 Settings of Capture Edge ............................................................................................................................ 126 Buzzer Frequency of 16-Bit Timer............................................................................................................... 128 Operation Modes ......................................................................................................................................... 131 8-Bit Timer Configuration ............................................................................................................................ 132 Interval Time of Timer 50 ............................................................................................................................ 144 Interval Time of Timer 60 ............................................................................................................................ 144 Square-Wave Output Range of Timer 50 (During fX = 5.0 MHz Operation) ................................................ 151 Square-Wave Output Range of Timer 60 (During fX = 5.0 MHz Operation) ................................................ 152 Interval Time with 16-Bit Resolution (During fX = 5.0 MHz Operation) ........................................................ 154 Square-Wave Output Range with 16-Bit Resolution (During fX = 5.0 MHz Operation)................................ 158 Interval Generated Using the Interval Timer ............................................................................................... 172 Watch Timer Configuration.......................................................................................................................... 172 Interval Time of Interval Timer..................................................................................................................... 174 Watchdog Timer Runaway Detector Time................................................................................................... 177 Interval Time................................................................................................................................................ 177 Configuration of Watchdog Timer................................................................................................................ 178 Watchdog Timer Runaway Detection Time ................................................................................................. 181 Interval Time of Interval Timer..................................................................................................................... 182 Configuration of 8-Bit A/D Converter ........................................................................................................... 183 Configuration of 10-Bit A/D Converter ......................................................................................................... 197 22 User's Manual U15075EJ1V0UM00 LIST OF TABLES (2/2) Table No. 12-1 12-2 12-3 12-4 12-5 12-6 12-7 13-1 13-2 13-3 13-4 13-5 13-6 13-7 14-1 14-2 14-3 15-1 15-2 15-3 15-4 16-1 17-1 17-2 17-3 17-4 18-1 19-1 Title Page Configuration of Serial Interface 20............................................................................................................. 211 Serial Interface 20 Operating Mode Settings .............................................................................................. 217 Example of Relationships Between System Clock and Baud Rate............................................................. 220 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H)....... 221 Example of Relationships Between System Clock and Baud Rate............................................................. 229 Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H)....... 230 Receive Error Causes ................................................................................................................................. 235 Number of Segment Outputs and Maximum Number of Pixels................................................................... 247 Configuration of LCD Controller/Driver........................................................................................................ 247 Frame Frequencies (Hz) ............................................................................................................................. 251 COM Signals ............................................................................................................................................... 254 LCD Drive Voltage....................................................................................................................................... 254 Select and Deselect Voltages (COM0 to COM2) ........................................................................................ 256 Select and Deselect Voltages (COM0 to COM3) ........................................................................................ 259 Interrupt Source List.................................................................................................................................... 264 Flags Corresponding to Interrupt Request Signal Name............................................................................. 266 Time from Generation of Maskable Interrupt Request to Servicing ............................................................ 274 HALT Mode Operating Status ..................................................................................................................... 281 Operation After Releasing HALT Mode....................................................................................................... 283 STOP Mode Operating Status..................................................................................................................... 284 Operation After Releasing STOP Mode ...................................................................................................... 286 Hardware Status After Reset....................................................................................................................... 289 Differences Between PD78F9436, 78F9456 and Mask ROM Versions .................................................... 291 Communication Mode ................................................................................................................................. 292 Functions of Flash Memory Programming .................................................................................................. 293 Example of Settings for PG-FP3 ................................................................................................................. 295 Selection of Mask Option for Pins ............................................................................................................... 297 Operand Identifiers and Description Methods ............................................................................................. 299 User's Manual U15075EJ1V0UM00 23 [MEMO] 24 User's Manual U15075EJ1V0UM00 CHAPTER 1 GENERAL 1.1 Features * ROM and RAM capacities Item Program Memory (ROM) Data Memory Internal High-Speed RAM 512 bytes LCD Display RAM Part Number PD789425, 789435 PD789426, 789436 PD78F9436 PD789445, 789455 PD789446, 789456 PD78F9456 Mask ROM 8 KB 16 KB 5 bytes Flash memory Mask ROM 16 KB 12 KB 16 KB 15 bytes Flash memory * Minimum instruction execution time can be changed from high-speed (0.4 s: @ 5.0 MHz operation with main system clock) to ultra-low-speed (122 s: @ 32.768 kHz operation with subsystem clock) * I/O ports: 40 (PD789426, 789436 Subseries) 30 (PD789446, 789456 Subseries) * Timer: 5 channels * * * * 16-bit timer: 8-bit timer: Watch timer: 1 channel 2 channels 1 channel Watchdog timer: 1 channel 6 channels (PD789426, 789446 Subseries) * A/D converter: 8-bit resolution: 10-bit resolution: 6 channels (PD789436, 789456 Subseries) * Serial interface: 1 channel * LCD controller/driver Segment signals: 5, common signals: 4 (PD789426, 789436 Subseries) Segment signals: 15, common signals: 4 (PD789446, 789456 Subseries) * Vectored interrupt sources: 15 * Power supply voltage: VDD = 1.8 to 5.5 V * Operating ambient temperature: TA = -40 to +85C 1.2 Applications Portable audio, cameras, healthcare equipment, etc. User's Manual U15075EJ1V0UM00 25 CHAPTER 1 GENERAL 1.3 Ordering Information Part Number Package 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) 64-pin plastic TQFP (12 x 12 mm) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Flash memory Flash memory PD789425GK-xxx-9ET PD789426GK-xxx-9ET PD789435GK-xxx-9ET PD789436GK-xxx-9ET PD789445GK-xxx-9ET PD789446GK-xxx-9ET PD789455GK-xxx-9ET PD789456GK-xxx-9ET PD78F9436GK-9ET PD78F9456GK-9ET Remark xxx indicates ROM code suffix. 26 User's Manual U15075EJ1V0UM00 CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) 1.4.1 Pin configuration of PD789426, 789436 Subseries (Top view) 64-pin plastic TQFP (fine pitch) (12 x 12) PD789425GK-xxx-9ET PD789426GK-xxx-9ET PD789435GK-xxx-9ET PD789436GK-xxx-9ET PD78F9436GK-9ET P20 P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INTP0/CPT90 P31/INTP1/TO50/TMI60 P32/INTP2/TO60 P33/INTP3/TO61 P10 P11 AVSS P60/ANI0 P61/ANI1 P50 P51 P52 P53 IC(VPP) XT1 XT2 VDD VSS X1 X2 RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 AVDD P72 P71 P70 P81 P80 P97 P96 P95 P94 P93 P92 Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. Remark The parenthesized values apply to the PD78F9436. CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 P90 P91 User's Manual U15075EJ1V0UM00 27 CHAPTER 1 GENERAL 1.4.2 Pin configuration of PD789446, 789456 Subseries (Top view) 64-pin plastic TQFP (fine pitch) (12 x 12) PD789445GK-xxx-9ET PD789446GK-xxx-9ET PD789455GK-xxx-9ET PD789456GK-xxx-9ET PD78F9456GK-9ET P20 P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INTP0/CPT90 P31/INTP1/TO50/TMI60 P32/INTP2/TO60 P33/INTP3/TO61 P10 P11 AVSS P60/ANI0 P61/ANI1 P50 P51 P52 P53 IC(VPP) XT1 XT2 VDD VSS X1 X2 RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 AVDD P72 P71 P70 S14 S13 S12 S11 S10 S9 S8 S7 Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. Remark The parenthesized values apply to the PD78F9456. 28 CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 User's Manual U15075EJ1V0UM00 CHAPTER 1 GENERAL ANI0 to ANI5: ASCK20: AVDD: AVSS: BZO90: CAPH, CAPL: Analog input Asynchronous serial input Analog power supply Analog ground Buzzer output LCD power supply capacitance control P90 to P97 RESET: RxD20: SS20: Note 1 : Port 9 Reset Receive data Serial chip select Note 2 S0 to S4, S5 to S14 SCK20: SI20: SO20: TMI60: : Segment output Serial clock Serial input Serial output Timer input COM0 to COM3: Common output CPT90: IC: Capture trigger input Internally connected INTP0 to INTP3: External interrupt input KR0 to KR3: P00 to P03: P10, P11: P20 to P26: P30 to P33: P50 to P53: P60 to P65: P70 to P72: P80, P81 Note 1 TO90, TO50, TO60, TO61: TxD20: VDD: VLC0 to VLC2: VPP: VSS: X1, X2: XT1, XT2: Timer output Transmit data Power supply LCD power supply Programming power supply Ground Crystal (main system clock) Crystal (subsystem clock) Key return Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 7 : Port 8 Notes 1. PD789426, 789436 Subseries only 2. PD789446, 789456 Subseries only User's Manual U15075EJ1V0UM00 29 CHAPTER 1 GENERAL 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 28-pin PD789046 PD789026 PD789074 PD789014 PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A Inverter control PD789177Y PD789167Y PD789167 with enhanced A/D converter PD789104A with enhanced timer PD789146 with enhanced A/D converter PD789104A with added EEPROMTM PD789124A with enhanced A/D converter RC oscillation version of the PD789104A PD789104A with enhanced A/D converter PD789026 with added A/D converter and multiplier 44-pin PD789842 On-chip inverter controller and UART VFD drive 78K/0S Series 52-pin PD789871 Total display outputs: 25 LCD drive 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin PD789488 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 Dot LCD drive A/D converter and on-chip voltage booster type LCD (28 x 4) PD789407A with enhanced A/D converter A/D converter and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter A/D converter and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D A/D converter and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 On-chip voltage booster type LCD (24 x 4) 144-pin 88-pin PD789835 PD789830 Segment/common outputs: 96 Segments: 40, commons: 16 ASSP 80-pin 52-pin 52-pin 64-pin 44-pin 44-pin 20-pin 20-pin PD789477 PD789467 PD789327 PD789803 PD789800 PD789840 PD789861 PD789860 PD789488 with added remote control receiver and resistance division type LCD For remote controller, with A/D converter and on-chip voltage booster type LCD For remote controller, with SIO and resistance division type LCD For PC keyboard, on-chip USB HUB function For PC keyboard, on-chip USB function For keypad, on-chip POC RC oscillation version of the PD789860 For keyless entry, on-chip POC and key return circuit 30 User's Manual U15075EJ1V0UM00 CHAPTER 1 GENERAL The major functional differences among the subseries are listed below. Function ROM Capacity Subseries Name Small-scale package, generalpurpose applications Small-scale package, generalpurpose applications and A/D converter 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D - - Serial Interface 1 ch (UART: 1 ch) VDD I/O MIN. Value 34 1.8 V Remarks PD789046 PD789026 PD789074 PD789014 PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A PD789842 PD789871 PD789488 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306 16 K 4 K to 16 K 2 K to 8 K 2 K to 4 K 16 K to 24 K 1 ch 1 ch 1 ch - 1 ch - 24 2 ch 3 ch - 1 ch 1 ch - - 8 ch - 4 ch - 4 ch - 4 ch 8 ch - 4 ch - 4 ch - 4 ch - - - 8 ch 7 ch 7 ch 2 ch - 6 ch - 6 ch - 6 ch - 6 ch - 2 ch (UART: 1 ch) 23 RC-oscillation version - 40 1 ch (UART: 1 ch) 1 ch 2 ch (UART: 1 ch) 1 ch (UART: 1 ch) 30 4.0 V 33 2.7 V 45 1.8 V 43 - - - 1 ch (UART: 1 ch) 22 31 - 8 K to 16 K 1 ch 20 On-chip EEPROM RC-oscillation version - 2 K to 8 K Inverter control VFD drive LCD drive 8 K to 16 K 4 K to 8 K 32 K 12 K to 24 K 12 K to 16 K 3 ch 3 ch 3 ch Note - 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 8 ch - - 30 8 K to 16 K - Dot LCD drive PD789835 PD789830 24 K to 60 K 24 K 24 K 4 K to 24 K 6 ch 1 ch 3 ch 2 ch - 1 ch 1 ch - 1 ch 1 ch 3 ch - - 1 ch (UART: 1 ch) 28 1.8 V 30 2.7 V - ASSP PD789477 PD789467 PD789327 PD789800 PD789840 PD789861 1 ch 1 ch 8 ch 1 ch - - 2 ch (UART: 1 ch) - 1 ch 2 ch (USB: 1 ch) 45 1.8 V On-chip LCD 18 21 31 4.0 V 29 2.8 V - 8K - 4 ch 1 ch - 4K - 14 1.8 V RC-oscillation version, on-chip EEPROM On-chip EEPROM PD789860 Note 10-bit timer: 1 channel User's Manual U15075EJ1V0UM00 31 CHAPTER 1 GENERAL 1.6 Block Diagram 1.6.1 Block diagram of PD789426, 789436 Subseries TO50/TMI60/ P31 TO60/P32 TO61/P33 TMI60/TO50/ P31 TO90/P26 CPT90/P30 BZO90/P21 Cascaded 8-bit timer 50 16-bit Port 0 Port 1 Port 2 P00 to P03 P10, P11 P20 to P26 P30 to P33 P50 to P53 P60 to P65 P70 to P72 P80, P81 P90 to P97 RESET X1 X2 XT1 XT2 INTP0/P30 8-bit event timer/event counter 60 counter timer/ 16-bit timer 90 Port 3 Port 5 ROM (flash memory) Port 6 Port 7 Watch timer 78K/0S CPU core Watchdog timer ANI0/P60 to ANI5/P65 AVDD AVSS SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25 SS20/P22 S0 to S4 COM0 to COM3 VLC0 to VLC2 CAPH CAPL A/D converter Port 8 Port 9 RAM RAM space for LCD data System control Serial Iinterface 20 LCD controller driver Interrupt control INTP1/P31 INTP2/P32 INTP3/P33 KR0/P00 to KR3/P03 VDD VSS IC (VPP) Remarks 1. The internal ROM capacity varies depending on the product. 2. The parenthesized values apply to the PD78F9436. 32 User's Manual U15075EJ1V0UM00 CHAPTER 1 GENERAL 1.6.2 Block diagram of PD789446, 789456 Subseries TO50/TMI60/ P31 TO60/P32 TO61/P33 TMI60/TO50/ P31 TO90/P26 CPT90/P30 BZO90/P21 Cascaded 8-bit timer 50 16-bit Port 0 Port 1 Port 2 P00 to P03 P10, P11 P20 to P26 P30 to P33 P50 to P53 P60 to P65 P70 to P72 P80, P81 P90 to P97 RESET X1 X2 XT1 XT2 INTP0/P30 8-bit event timer/event counter 60 counter timer/ 16-bit timer 90 Port 3 Port 5 ROM (flash memory) Port 6 Port 7 Watch timer 78K/0S CPU core Watchdog timer ANI0/P60 to ANI5/P65 AVDD AVSS SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25 SS20/P22 S0 to S4 COM0 to COM3 VLC0 to VLC2 CAPH CAPL A/D converter Port 8 Port 9 RAM RAM space for LCD data System control Serial Iinterface 20 LCD controller driver Interrupt control INTP1/P31 INTP2/P32 INTP3/P33 KR0/P00 to KR3/P03 VDD VSS IC (VPP) Remarks 1. The internal ROM capacity varies depending on the product. 2. The parenthesized values apply to the PD78F9456. User's Manual U15075EJ1V0UM00 33 CHAPTER 1 GENERAL 1.7 Overview of Functions Item PD789425, PD789426, PD78F9436 PD789445, PD789446, PD78F9456 789435 789436 789455 789456 Mask ROM Flash memory 16 KB Mask ROM Flash memory 16 KB Internal memory ROM 12 KB High-speed RAM LCD display RAM Minimum instruction execution time 512 bytes 5 bytes 12 KB 15 bytes * 0.4 s/1.6 s (@ 5.0 MHz operation with main system clock) * 122 s (@ 32.768 kHz operation with subsystem clock) 8 bits x 8 registers * 16-bit operations * Bit manipulations (such as set, reset, and test) Total: * CMOS I/O: * CMOS input: * N-ch open-drain: 40 30 6 4 1 channel 2 channels 1 channel 1 channel Total: * CMOS I/O: * CMOS input: * N-ch open-drain: 30 20 6 4 General-purpose registers Instruction set I/O ports Timers * * * * 16-bit timer: 8-bit timer: Watch timer: Watchdog timer: A/D converter * 8-bit resolution x 6 channels (PD789426, 789446 Subseries) * 10-bit resolution x 6 channels (PD789436, 789456 Subseries) Switchable between 3-wire serial I/O mode and UART mode: 1 channel * Segment signal outputs: * Common signal outputs: Maskable Non-maskable Internal: 9, external: 5 Internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C 64-pin plastic TQFP (fine pitch) (12 x 12) 5 max. 4 max. * Segment signal outputs: * Common signal outputs: 15 max. 4 max. Serial interfaces LCD controller/driver Vectored interrupt sources Power supply voltage Operating ambient temperature Package 34 User's Manual U15075EJ1V0UM00 CHAPTER 1 GENERAL An outline of the timer is shown below. 16-Bit Timer Operation mode Interval timer External event counter Timer outputs Square-wave outputs Capture Interrupt sources - - 8-Bit Timer 50 1 channel - 8-Bit Timer 60 1 channel 1 channel Watch Timer Watchdog Timer 1 channel - Note 2 1 channel - Note 1 Function 1 - 1 1 2 2 - - - - 1 input 1 - 1 - 1 - 1 - 1 Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or interval timer function. User's Manual U15075EJ1V0UM00 35 [MEMO] 36 User's Manual U15075EJ1V0UM00 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions (1) Port pins (1/2) I/O I/O Function Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00). Port 1. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0). Port 2. 7-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B2 (PUB2). After Reset Input Alternate Function KR0 to KR3 Pin Name P00 to P03 P10 to P13 I/O Input - P20 P21 P22 P23 P24 P25 P26 P30 P31 I/O Input BZO90 SS20 - SCK20/ASCK20 SO20/TxD20 SI20/RxD20 TO90 I/O P32 P33 P50 to P53 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B3 (PUB3). Input INTP0/CPT90 INTP1/TO50/ TMI60 INTP2/TO60 INTP3/TO61 Port 5. 4-bit N-ch open-drain I/O port. Input/output can be specified in 1-bit units. For a mask ROM version, an on-chip pull-up resistor can be specified by the mask option. Port 6. 6-bit input port. Port 7. 3-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B7 (PUB7). Input - P60 to P65 Input Input ANI0 to ANI5 - P70 to P72 I/O Input User's Manual U15075EJ1V0UM00 37 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) I/O I/O Function Port 8. 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B8 (PUB8). Port 9. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B9 (PUB9). After Reset Input Alternate Function - Pin Name P80, P81 Note P90 to P97 Note I/O Input - Note PD789426, 789436 Subseries only 38 User's Manual U15075EJ1V0UM00 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins I/O Input Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P30/CPT90 P31/TO50/TMI60 P32/TO60 P33/TO61 Input Input I/O Input Output Input Input Output Output Input Output Output Output Input Input Output Note Pin Name INTP0 INTP1 INTP2 INTP3 KR0 to KR3 SS20 SCK20 SI20 SO20 ASCK20 RxD20 TxD20 TO90 CPT90 TO50 TO60 TO61 TMI60 ANI0 to ANI5 S0 to S4 S5 to S14 Key return signal detection Serial interface (SIO20) chip select Serial interface 20 serial clock input/output Serial interface 20 of SIO20 serial data input Serial interface 20 of SIO20 serial data output Serial clock input for asynchronous serial interface Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface 16-bit timer (TM90) output Capture edge input 8-bit timer (TM50) output 8-bit timer (TM60) output Input Input Input Input Input Input Input Input Input Input Input Input Input P00 to P03 P22 P23/ASCK20 P25/RxD20 P24/TxD20 P23/SCK20 P25/SI20 P24/SO20 P26 P30/INTP0 P31/INTP1/TMI40 P32/INTP2 P33/INTP33 P31/INTP1/TO50 P60 to P65 *-* *-* - *-* *-* *-* *-* *-* *-* *-* *-* - - - - - - *-* *-* *-* *-* *-* External count clock input to timer 40 A/D converter analog input LCD controller/driver segment signal output Input Input Output Output Output LCD controller/driver common signal output LCD driving voltage Capacitor connection pin for LCD drive COM0 to COM3 Output VLC0 to VLC2 CAPH CAPL X1 X2 XT1 XT2 RESET VDD VSS AVDD AVSS IC VPP - - - Input - Input - Input - - - - - - Output - - - Connecting crystal resonator for main system clock oscillation - - Connecting crystal resonator for subsystem clock oscillation - - System reset input Positive power supply Ground potential A/D converter analog potential A/D converter analog ground potential Internally connected. Connect directly to VSS. Sets flash memory programming mode. Applies high voltage when a program is written or verified. Connect directly to VSS in normal operation mode. Input Note PD789446, 789456 Subseries only User's Manual U15075EJ1V0UM00 39 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port. In addition, these pins enable key return signal detection. Port 0 can be specified in the following operation modes in 1-bit units. (1) Port mode These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) in port units. (2) Control mode In this mode, P00 to P03 function as key return signal detection pins (KR0 to KR3). 2.2.2 P10, P11 (Port 1) These pins constitute a 2-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) in port units. 2.2.3 P20 to P26 (Port 2) These pins constitute a 7-bit I/O port. In addition, these pins enable buzzer output, timer output, serial interface data I/O, and serial clock I/O. Port 2 can be specified in the following operation modes in 1-bit units. (1) Port mode In this mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set in the input or output port mode in 1bit units by port mode register 2 (PM2). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register B2 (PUB2) in 1-bit units. (2) Control mode In this mode, P20 to P26 function as the buzzer output, timer output, serial interface data I/O, and serial clock I/O. (a) Buzzer output This is the buzzer output pin of 16-bit timer 90. (b) TO90 This is the timer output pin of 16-bit timer 90. (c) SI20, SO20 These are the serial data I/O pins of the serial interface. (d) SCK20 This is the serial clock I/O pin of the serial interface. (e) RxD20, TxD20 These are the serial data I/O pins of the asynchronous serial interface. 40 User's Manual U15075EJ1V0UM00 CHAPTER 2 PIN FUNCTIONS (f) ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be set according to the functions to be used. For the details of the setting, refer to Table 12-2 Settings of Serial Interface 20 Operating Mode. 2.2.4 P30 to P33 (Port 3) These pins constitute a 4-bit I/O port. In addition, they also function as timer I/O and external interrupt input. Port 3 can be specified in the following operation mode in 1-bit units. (1) Port mode In this mode, P30 to P33 functions as a 4-bit I/O port. Port 3 can be set in the input or output port mode in 1-bit units by port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register B3 (PUB3) in 1-bit units. (2) Control mode In this mode, P30 to P33 function as timer I/O and external interrupt input. (a) TMI60 This is the external clock input pin to timer 60. (b) TO50, TO60, TO61 These are the timer output pins of timer 50 and timer 60 (c) CPT90 This is the capture edge input pin of 16-bit timer 90. (d) INTP0 to INTP3 These are external interrupt input pins for which valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.5 P50 to P53 (Port 5) These pins function as a 4-bit N-ch open-drain I/O port. Port 5 can be set in the input or output port mode in 1-bit units by port mode register 5 (PM5). In the mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option. 2.2.6 P60 to P65 (Port 6) This is a 6-bit input-only port. In addition to a general-purpose input port function, it has an A/D converter input function. (1) Port mode In this mode, P60 to P65 function as 6-bit input-only port. (2) Control mode In this mode, P60 to P65 function as analog inputs (ANI0 to ANI5) of A/D converter. User's Manual U15075EJ1V0UM00 41 CHAPTER 2 PIN FUNCTIONS 2.2.7 P70 to P72 (Port 7) These pins constitute a 3-bit I/O port. Port 7 can be set in the input or output mode in 1-bit units by port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register B7 (PUB7) in port units. 2.2.8 P80, P81 (Port 8) Note These pins constitute a 2-bit I/O port. Port 8 can be set in the input or output mode in 1-bit units by port mode register 8 (PM8). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register B8 (PUB8) in port units. Note Only the PD789426 and PD789436 Subseries. 2.2.9 P90 to P97 (Port 9) Note These pins constitute an 8-bit I/O port. Port 9 can be set in the input or output mode in 1-bit units by port mode register 9 (PM9). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register B9 (PUB9) in port units. Note Only the PD789426 and PD789436 Subseries. 2.2.10 S0 to S14 Note These pins are segment signal output pins for the LCD controller/driver. Note S0 to S4 in the case of the PD789426 and 789436 Subseries 2.2.11 COM0 to COM3 These pins are common signal output pins for the LCD controller/driver. 2.2.12 VLC0 to VLC2 These pins are power supply voltage pins to drive the LCD. 2.2.13 CAPH, CAPL These pins are capacitor connection pins to drive the LCD. 2.2.14 RESET This pin inputs an active-low system reset signal. 2.2.15 X1, X2 These pins are used to connect a crystal resonator for main system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.16 XT1, XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation. To supply an external clock, input the clock to XT1 and input the inverted signal to XT2. 42 User's Manual U15075EJ1V0UM00 CHAPTER 2 PIN FUNCTIONS 2.2.17 VDD This is the positive power supply pin. 2.2.18 VSS This is the ground pin. 2.2.19 VPP (PD78F9436, 78F9456 only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Directly connect this pin to VSS in the normal operation mode. 2.2.20 IC (mask ROM version only) The IC (Internally Connected) pin is used to set the PD789426, 789436, 789446, and 789456 Subseries in the test mode before shipment. In the normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as possible. If a potential difference is generated between the IC pin and VSS pin due to a long wiring length, or an external noise superimposed on the IC pin, the user program may not run correctly. * Directly connect the IC pin to the VSS pin. VSS IC Keep short User's Manual U15075EJ1V0UM00 43 CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, see Figure 2-1. Table 2-1. Types of Pin Input/Output Circuits Pin Name I/O Circuit Type 8-A 5-A 8-A I/O Recommended Connection of Unused Pins P00/KR0 to P03/KR3 P10, P11 P20 P21/BZO90 P22/SS20 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO90 P30/INPT0/CPT90 P31/INPT1/TO50/TMI60 P32/INPT2/TO60 P33/INPT3/TO61 P50 to P53 (Mask ROM version) P50 to P53 (Flash memory version) P60/ANI0 to P65/ANI5 P70 to P72 P80, P81 Note 1 I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. Input: Independently connect to VSS via a resistor. Output: Leave open. 13-W Input: Independently connect to VDD via a resistor. Output: Leave open. 13-V 9-C 5-A Input I/O Connect directly to VDD or VSS. Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P90 to P97 S0 to S4 Note 1 Note 1 17 Output Leave open. S0 to S14 Note 2 COM0 to COM3 VLC0 to VLC2 CAPH, CAPL XT1 XT2 AVSS AVDD RESET IC VPP 18 - *-* Input - Connect to VSS. Leave open. Connect to VSS. Connect to VDD. 2 - Input *-* Connect directly to VSS. - Notes 1. When using the PD789426 and 789436 Subseries 2. When using the PD789446 and 789456 Subseries 44 User's Manual U15075EJ1V0UM00 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin Input/Output Circuits Type 2 Type 13-V IN/OUT Output data Output disable N-ch IN VSS Schmitt-triggered input with hysteresis characteristics Input enable Middle-voltage input buffer Type 5-A VDD Type 13-W VDD Pull-up enable VDD Data P-ch IN/OUT Output disable N-ch VSS P-ch Pull-up resistor (mask option) IN/OUT Output data Output disable N-ch VSS Input enable Middle-voltage input buffer Input enable Type 8-A VDD Type 17 VLC0 Pull-up enable VDD Data P-ch IN/OUT Output disable N-ch VSS P-ch P-ch P-ch N-ch P-ch VLC1 SEG data N-ch VLC2 N-ch P-ch N-ch OUT Type 9-C Type 18 VLC0 P-ch P-ch N-ch P-ch N-ch OUT IN P-ch N-ch AVSS Comparator + VLC1 VREF (Threshold voltage) COM data N-ch P-ch N-ch N-ch P-ch Input enable VLC2 User's Manual U15075EJ1V0UM00 45 [MEMO] 46 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The PD789426, 789436, 789446, and 789456 Subseries can access 64 KB of memory space. Figures 3-1 through 3-6 show the memory maps. Figure 3-1. Memory Map (PD789425, 789435) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH FA05H FA04H Data memory space Reserved LCD display RAM 5 x 4 bits FA00H F9FFH Reserved 3000H 2FFFH Program area 2FFFH Program memory space Internal ROM 12288 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Vector table area User's Manual U15075EJ1V0UM00 47 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD789426, 789436) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH FA05H FA04H Data memory space Reserved LCD display RAM 5 x 4 bits FA00H F9FFH 4000H 3FFFH Reserved 3FFFH Program area Program memory space Internal ROM 16384 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Vector table area 48 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD78F9436) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH FA05H FA04H Data memory space LCD display RAM 5 x 4 bits FA00H F9FFH 4000H 3FFFH Program area 3FFFH Reserved Reserved Program memory space Flash memory 16384 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Vector table area User's Manual U15075EJ1V0UM00 49 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD789445, 789455) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH FA0FH FA0EH Data memory space Reserved LCD display RAM 15 x 4 bits FA00H F9FFH 3000H 2FFFH Reserved 2FFFH Program area Program memory space Internal ROM 12288 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Vector table area 50 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (PD789446, 789456) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH FA0FH FA0EH Data memory space Reserved LCD display RAM 15 x 4 bits FA00H F9FFH 4000H 3FFFH Reserved 3FFFH Program area Program memory space Internal ROM 16384 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Vector table area User's Manual U15075EJ1V0UM00 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map (PD78F9456) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH FA0FH FA0EH Data memory space LCD display RAM 15 x 4 bits FA00H F9FFH 4000H 3FFFH Program area 3FFFH Reserved Reserved Program memory space Flash memory 16384 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H 0000H 0000H Vector table area 52 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789426, 789436, 789446, and 789456 Subseries provide internal ROM (or flash memory) with the following capacity for each product. Table 3-1. Internal ROM Capacity Part Number Structure Internal ROM Capacity 12288 x 8 bits 16384 x 8 bits 16384 x 8 bits PD789425, 789435, 789445, 789455 PD789426, 789436, 789446, 789456 PD78F9436, 78F9456 Mask ROM Flash memory The following areas are allocated to the internal program memory space. (1) Vector table area The 34-byte area of addresses 0000H to 0021H is reserved as a vector table area. This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16-bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 3-2. Vector Table Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH 0012H Interrupt Request RESET input INTWDT INTP0 INTP1 INTP2 INTP3 INTSR20/INTCSI20 INTST20 Vector Table Address 0014H 0016H 0018H 001AH 001CH 001EH 0020H Interrupt Request INTWTI INTTM90 INTTM50 INTTM60 INTAD0 INTWT INTKR00 (2) CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. User's Manual U15075EJ1V0UM00 53 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space The PD789426, 789436, 789446, and 789456 Subseries products incorporate the following RAM. (1) Internal high-speed RAM Internal high-speed RAM is incorporated in the area between FD00H and FEFFH. The internal high-speed RAM is also used as a stack. (2) LCD display RAM LCD display RAM is incorporated. The LCD display RAM can also be used as ordinary RAM. Each subseries incorporates LCD display RAM with the following capacity. Table 3-3. LCD Display RAM Capacity Subseries Name Area FA00H to FA04H FA00H to FA0EH Capacity 5 x 4 bits 15 x 4 bits PD789426, 789436 Subseries PD789446, 789456 Subseries 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated in the area between FF00H to FFFFH (see Table 3-4). 54 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The PD789426, 789436, 789446, and 789456 Subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area (FD00H to FFFFH) especially, specific addressing modes that correspond to the particular function an area, such as the special function registers are available. Figures 3-7 through 3-12 show the data memory addressing modes. Figure 3-7. Data Memory Addressing (PD789425, 789435) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Reserved FA05H FA04H LCD display RAM 5 x 4 bits FA00H F9FFH Reserved 3000H 2FFFH Internal ROM 12288 x 8 bits 0000H Direct adressing Register indirect addressing Based addressing User's Manual U15075EJ1V0UM00 55 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing (PD789426, 789436) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Reserved FA05H FA04H LCD display RAM 5 x 4 bits FA00H F9FFH Reserved 4000H 3FFFH Internal ROM 16384 x 8 bits Direct addressing Register indirect addressing Based addressing 0000H 56 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing (PD78F9436) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Reserved FA05H FA04H LCD display RAM 5 x 4 bits FA00H F9FFH Reserved 4000H 3FFFH Flash memory 16384 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing User's Manual U15075EJ1V0UM00 57 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing (PD789445, 789455) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 x 4 bits FA00H F9FFH Reserved 3000H 2FFFH Internal ROM 12288 x 8 bits Direct addressing Register indirect addressing Based addressing 0000H 58 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data Memory Addressing (PD789446, 789456) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 x 4 bits FA00H F9FFH Reserved 4000H 3FFFH Internal ROM 16384 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing User's Manual U15075EJ1V0UM00 59 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Data Memory Addressing (PD78F9456) FFFFH Special function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH Short direct addressing SFR addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH FD00H FCFFH Reserved FA0FH FA0EH LCD display RAM 15 x 4 bits FA00H F9FFH Reserved 4000H 3FFFH Flash memory 16384 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing 60 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The PD789426, 789436, 789446, and 789456 Subseries provide the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-13. Program Counter Configuration 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. The program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets PSW to 02H. Figure 3-14. Program Status Word Configuration 7 PSW IE Z 0 AC 0 0 1 0 CY User's Manual U15075EJ1V0UM00 61 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgement operations of the CPU. When 0, IE is set to the interrupt disable status (DI), and interrupt requests other than non-maskable interrupt are all disabled. When 1, IE is set to the interrupt enable status (EI). Interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources. IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (d) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. 62 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-15. Stack Pointer Configuration 15 0 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP SP15 SP14 SP13 SP12 SP11 SP10 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-16 and 3-17. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-16. Data to Be Saved to Stack Memory PUSH rp instruction CALL, CALLT instructions SP SP SP _ 2 SP _ 2 SP _ 1 SP Lower register pairs Higher register pairs SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 PSW Interrupt Figure 3-17. Data to Be Restored from Stack Memory POP rp instruction RET instruction RETI instruction SP SP + 1 SP SP + 2 Lower register pairs Higher register pairs SP SP SP + 1 SP + 2 PC7 to PC0 PC15 to PC8 SP SP + 1 SP + 2 SP SP + 3 PC7 to PC0 PC15 to PC8 PSW User's Manual U15075EJ1V0UM00 63 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). General-purpose registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, or HL) or absolute names (R0 to R7 and RP0 to RP3). Figure 3-18. General-Purpose Register Configuration (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 0 7 0 64 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register type. The manipulatable bits can be specified as follows. * 1-bit manipulation Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). manipulation can also be specified with an address. * 16-bit manipulation Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. addressing an address, describe an even address. Table 3-4 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the implemented special function registers. The symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called "sfrbit.h" of the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special function register in question can be read or written. R/W: R: W: Read/write Read only Write only When This * Bit manipulation unit Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated. * After reset Indicates the status of the special function register when the RESET signal is input. User's Manual U15075EJ1V0UM00 65 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Register List (1/2) Address Special Function Register (SFR) Name Symbol R/W Bit Manipulation Unit 1 Bit FF00H FF01H FF02H FF03H FF05H FF06H FF07H FF08H FF09H FF0CH FF0DH FF0EH FF0FH FF10H Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 7 Port 8 Port 9 Note 1 After Reset 8 Bits 16 Bits - - - - - - - - - Notes 3, 4 P0 P1 P2 P3 P5 P6 P7 P8 P9 CR60 CR50 TM60 TM50 TXS20 SIO20 RXB20 ADCR0 Note 5 R/W 00H R R/W Note 1 8-bit compare register 60 8-bit compare register 50 8-bit timer counter 60 8-bit timer counter 50 Transmit shift register 20 Receive buffer register 20 CR6 Note 2 W - - Undefined TM6 Note 2 R - - Notes 3, 4 00H W R R - - - - - Notes 3 FFH Undefined 0000H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF20H FF21H FF22H FF23H FF25H A/D conversion result register 0 16-bit compare register 90 CR90 Note 2 W - - Notes 3, 4 FFFFH 16-bit timer counter 90 TM90 Note 2 R - - Notes 3, 4 0000H 16-bit capture register 90 TCP90 Note 2 - - Note 3 Undefined Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 5 PM0 PM1 PM2 PM3 PM5 R/W - - - - - FFH Notes 1. PD789426 and 789436 Subseries only. 2. Name of SFR dedicated for 16-bit access. 3. Only in short direct addressing, 16-bit access is possible. 4. These are 16-bit access dedicated registers, however, 8-bit access is possible. When performing 8-bit access, access using direct addressing. 5. When used as an 8-bit A/D converter (PD789426 and 789446 Subseries), only 8-bit access is possible. In this case, the address is FF15H. When used as a 10-bit A/D converter (PD789436 and 789456 Subseries), only 16-bit access is possible. When the PD78F9436, a flash memory version of the PD789425 or PD789426, is used, this register can be accessed in 8-bit units. However, only an object file assembled with the PD789425 or PD789426 can be used. The same is also true for the PD78F9456, a flash memory version of the PD789445 or PD789446: this register can be accessed in 8-bit units, but only an object file assembled with the PD789445 or PD789446 can be used. 66 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Register List (2/2) Address Special Function Register (SFR) Name Symbol R/W Bit Manipulation Unit 1 Bit FF27H FF28H FF29H FF32H FF33H FF37H FF38H FF39H FF42H FF48H FF49H FF4AH FF4CH FF4DH FF4EH FF4FH FF70H FF71H FF72H FF73H FF80H FF84H FFB0H FFB2H FFB3H FFE0H FFE1H FFE4H FFE5H FFECH FFEDH FFF0H FFF2H FFF5H FFF7H FFF9H FFFAH FFFBH Port mode register 7 Port mode register 8 Port mode register 9 Note After Reset 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 04H 02H 00H FFH Undefined 00H 00H FFH PM7 PM8 PM9 PUB2 PUB3 PUB7 Note R/W - Note Pull-up resistor option register B2 Pull-up resistor option register B3 Pull-up resistor option register B7 Pull-up resistor option register B8 Pull-up resistor option register B9 PUB8 PUB9 WDCS TMC90 BZC90 WTM CRH60 TMC50 TMC60 TCA60 ASIM20 ASIS20 CSIM20 BRGC20 ADM0 ADS0 LCDM0 LCDC0 LCDVA0 IF0 IF1 MK0 MK1 INTM0 INTM1 SCKM CSS KRM00 PU0 WDTM OSTS PCC W R/W R R/W W R/W Note Watchdog timer clock select register 16-bit timer mode control register 90 Buzzer output control register 90 Watch timer mode control register 8-bit compare register H60 8-bit timer mode control register 50 8-bit timer mode control register 60 Carrier generator output control register 60 Asynchronous serial interface mode register 20 Asynchronous serial interface status register 20 Serial operation mode register 20 Baud rate generator control register 20 A/D converter mode register 0 Analog input channel specification register 0 LCD display mode register 0 LCD clock control register 0 LCD voltage amplification control register 0 Interrupt request flag register 0 Interrupt request flag register 1 Interrupt mask flag register 0 Interrupt mask flag register 1 External interrupt mode register 0 External interrupt mode register 1 Suboscillation mode register Subclock control register Key return mode register 00 Pull-up resistor option register 0 Watchdog timer mode register Oscillation stabilization time select register Processor clock control register - - - - - Note PD789426 and 789436 Subseries only. User's Manual U15075EJ1V0UM00 67 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. This means that information is relatively branched to a location between -128 and +127, from the start address of the next instruction when relative addressing is used. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC When S = 0, indicates all bits 0. When S = 1, indicates all bits 1. 0 6 0 0 ... PC is the start address of the next instruction of a BR instruction. 68 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 User's Manual U15075EJ1V0UM00 69 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH. [Illustration] 7 Instruction code 0 6 1 5 ta4-0 1 0 0 15 Effective address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective address + 1 High Addr. 15 PC 8 7 0 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 70 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 OP code 0 addr16 (Lower) addr16 (Higher) Memory User's Manual U15075EJ1V0UM00 71 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area. Ports that are frequently accessed in a program and the compare register of the timer/event counter are mapped in this area, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format] Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (Immediate data) [Illustration] 7 OP code saddr-offset 0 Short direct memory 15 Effective address 1 1 1 1 1 1 1 8 0 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. 72 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing. [Operand format] Identifier sfr Description Special function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 OP code sfr-offset 0 SFR 15 Effective Address 1 1 1 1 1 1 1 87 1 0 User's Manual U15075EJ1V0UM00 73 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 1 0 0 0 1 0 0 0 Register specification code INCW DE; When selecting the DE register pair for rp Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specification code 74 User's Manual U15075EJ1V0UM00 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [DE], [HL] [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 DE D 7 Addressed memory contents are transferred. 7 A 0 87 E 0 Memory address specified with register pair DE. 0 User's Manual U15075EJ1V0UM00 75 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [HL+byte] [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Only the internal high-speed RAM area can be addressed using stack addressing. [Description example] In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 76 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The PD789426, 789436, 789446, and 789456 Subseries provide the ports shown in Figures 4-1 and 4-2, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Types (PD789426, 789436 Subseries) P60 Port 6 P65 P00 Port 0 P03 P10 P11 P20 Port 1 P70 Port 7 P72 Port 2 Port 8 P80 P81 P26 P90 P30 Port 3 Port 9 P33 P50 P97 P53 Port 5 User's Manual U15075EJ1V0UM00 77 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Port Types (PD789446, 789456 Subseries) P50 Port 5 P53 P00 Port 0 P03 P10 P11 P20 P60 Port 1 Port 6 P65 Port 2 P70 Port 7 P72 P26 P30 Port 3 P33 78 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (1/2) Pin Name P00 to P03 I/O I/O Function Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00). Port 1. 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). Port 2. 7-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B2 (PUB2). After Reset Input Alternate Function KR0 to KR3 P10, P11 I/O Input - P20 P21 P22 P23 P24 P25 P26 P30 P31 P32 P33 P50 to P53 I/O Input BZO90 SS20 - SCK20/ASCK20 SO20/TxD20 SI20/RxD20 TO90 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B3 (PUB3). Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. For a mask ROM version, an on-chip pull-up resistor can be specified by a mask option. Port 6. 6-bit input port. Port 7. 3-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B7 (PUB7). Input INTP0/CPT90 INTP1/TO50/TMI60 INTP2/TO60 INTP3/TO61 I/O Input - P60 to P65 Input Input ANI0 to ANI5 - P70 to P72 I/O Input User's Manual U15075EJ1V0UM00 79 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions (2/2) Pin Name P80, P81 Note I/O I/O Function Port 8. 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B8 (PUB8). Port 9. 8-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B9 (PUB9). After Reset Input Alternate Function - P90 to P97 Note I/O Input - Note PD789426, 789436 Subseries only 4.2 Port Configuration Ports have the following hardware configuration. Table 4-2. Configuration of Port Item Control registers Configuration Port mode register (PMm: m = 0 to 3, 5, 7 to 9) Pull-up resistor option register (PU0, PUB2, PUB3, PUB7 to PUB9) Total: 40 (CMOS I/O: 30, CMOS input: 6, N-ch open-drain I/O: 4) Ports PD789426, 789436 Subseries PD789446, 789456 Subseries Total: 30 (CMOS I/O: 20, CMOS input: 6, N-ch open-drain I/O: 4) Pull-up resistors PD789426, 789436 Subseries PD789446, 789456 Subseries Total: 34 (software control: 30, mask option specification: 4) Total: 24 (software control: 20, mask option specification: 4) 80 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 This is a 4-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using the port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (PU0). Port 0 is set in the input mode when the RESET signal is input. Figure 4-3 shows a block diagram of port 0. Figure 4-3. Block Diagram of P00 to P03 VDD WRPUO PU00 RD Selector P-ch WRKRM00 KRM000 Internal bus WRPORT Output latch (P00 to P03) WRPM P00/KR0 to P03/KR3 PM00 to PM03 Alternate function KRM00: Key return mode register 00 PU0: PM: RD: WR: Pull-up resistor option register 0 Port mode register Port 0 read signal Port 0 write signal User's Manual U15075EJ1V0UM00 81 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0). This port is set in the input mode when the RESET signal is input. Figure 4-4 shows a block diagram of port 1. Figure 4-4. Block Diagram of P10 and P11 VDD WRPU0 PU01 RD P-ch Internal bus WRPORT Output latch (P10, P11) WRPM Selector P10, P11 PM10, PM11 PU0: PM: RD: WR: Pull-up resistor option register 0 Port mode register Port 1 read signal Port 1 write signal 82 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B2 (PUB2). The port is also used as the serial interface I/O, buzzer output, and timer output. This port is set in the input mode when the RESET signal is input. Figures 4-5 to 4-10 show block diagrams of port 2. Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set according to the function to be used. For how to set the latches, see Figure 12-2 Settings of Serial Interface 20 Operating Mode. Figure 4-5. Block Diagram of P20 VDD WRPUB2 PUB20 RD P-ch Internal bus WRPORT Output latch (P20) WRPM Selector P20 PM20 PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User's Manual U15075EJ1V0UM00 83 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P21 and P26 VDD WRPUB2 PUB21, PUB26 P-ch RD Selector Internal bus WRPORT Output latch (P21, P26) WRPM P21/BZO90, P26/TO90 PM21, PM26 Alternate function PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal 84 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P22 VDD WRPUB2 PUB22 P-ch Alternate function RD Internal bus WRPORT Output latch (P22) WRPM Selector P22/SS20 PM22 PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User's Manual U15075EJ1V0UM00 85 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P23 VDD WRPUB2 PUB23 P-ch Alternate function RD Internal bus WRPORT Output latch (P23) WRPM Selector P23/ASCK20/ SCK20 PM23 Alternate function PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal 86 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P24 VDD WRPUB2 PUB24 P-ch RD Selector Internal bus WRPORT Output latch (P24) WRPM P24/SO20/TxD20 PM24 Alternate function SS20 output PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal User's Manual U15075EJ1V0UM00 87 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P25 VDD WRPUB2 PUB25 P-ch Alternate function RD Internal bus Selector WRPORT Output latch (P25) WRPM P25/SI20/ RxD20 PM25 PUB2: PM: RD: WR: Pull-up resistor option register B2 Port mode register Port 2 read signal Port 2 write signal 88 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 4-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by using port mode register 3 (PM3). When using the P30 to P33 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B3 (PUB3). This port is also used as an external interrupt input, capture input, and timer I/O. This port is set in the input mode when the RESET signal is input. Figures 4-11 and 4-12 show block diagrams of port 3. Figure 4-11. Block Diagram of P30 VDD WRPUB3 PUB30 P-ch Alternate function RD Internal bus Selector WRPORT Output latch (P30) WRPM P30/INTP0/CPT90 PM30 PUB3: PM: RD: WR: Pull-up resistor option register B3 Port mode register Port 3 read signal Port 3 write signal User's Manual U15075EJ1V0UM00 89 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P31 to P33 VDD WRPUB3 PUB31 to PUB33 P-ch Alternate function RD Internal bus WRPORT Output latch (P31 to P33) WRPM Selector P31/INTP1/TO50/ TMI60, P32/INTP2/TO60, P33/INTP3/TO61 PM31 to PM33 Alternate function PUB3: PM: RD: WR: Pull-up resistor option register B3 Port mode register Port 3 read signal Port 3 write signal 90 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option. This port is set in the input mode when the RESET signal is input. Figure 4-13 shows a block diagram of port 5. Figure 4-13. Block Diagram of P50 to P53 RD VDD Internal bus Selector Mask option resistor Mask ROM version only. For flash memory version, a pull-up resistor is not incorporated. WRPORT Output latch (P50 to P53) N-ch P50 to P53 WRPM PM50 to PM53 PM: RD: WR: Port mode register Port 5 read signal Port 5 write signal User's Manual U15075EJ1V0UM00 91 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 This is an 8-bit input-only port. This port is also used as the analog input of an A/D converter. Figure 4-14 shows a block diagram of Port 6. Figure 4-14. Block Diagram of Port 6 RD Internal bus + A/D converter - P60/ANI0 to P65/ANI5 VREF 92 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 This is a 3-bit I/O port with an output latch. Port 7 can be specified in the input or output mode in 1-bit units by using port mode register 7 (PM7). When using the P70 to P72 pins as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B7 (PUB7). This port is set in the input mode when the RESET signal is input. Figure 4-15 shows a block diagram of Port 7. Figure 4-15. Block Diagram of P70 to P72 VDD WRPUB7 PUB70 to PUB72 P-ch RD Internal bus WRPORT Output latch (P70 to P72) Selector P70 to P72 WRPM PM70 to PM72 PUB7: Pull-up resistor option register B7 PM: RD: WR: Port mode register Port 7 read signal Port 7 write signal User's Manual U15075EJ1V0UM00 93 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 8 (PD789426, 789436 Subseries only) This is a 2-bit I/O port with an output latch. Port 8 can be specified in the input or output mode in 1-bit units by using port mode register 8 (PM8). When using pins P80 and P81 as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B8 (PUB8). This port is set in the input mode when the RESET signal is input. Figure 4-16 shows a block diagram of port 8. Figure 4-16. Block Diagram of P80 and P81 VDD WRPUB8 PUB80, PUB81 RD P-ch Internal bus WRPORT Output latch (P80, P81) WRPM Selector P80, P81 PM80, PM81 PUB8: Pull-up resistor option register B8 PM: RD: WR: Port mode register Port 8 read signal Port 8 write signal 94 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 9 (PD789426, 789436 Subseries only) This is an 8-bit I/O port with an output latch. Port 9 can be specified in the input or output mode in 1-bit units by using port mode register 9 (PM9). When using the pins of this port as input port pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B9 (PUB9). This port is set in the input mode when the RESET signal is input. Figure 4-17 shows a block diagram of port 9. Figure 4-17. Block Diagram of P90 to P97 VDD WRPUB9 PUB90 to PUB97 P-ch RD Internal bus WRPORT Output latch (P90 to P97) Selector P90 to P97 WRPM PM90 to PM97 PUB9: Pull-up resistor option register B9 PM: RD: WR: Port mode register Port 9 read signal Port 9 write signal User's Manual U15075EJ1V0UM00 95 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function The ports are controlled by the following two types of registers. * Port mode registers (PM0 to PM3, PM5, PM7 to PM9) * Pull-up resistor option registers (PU0, PUB2, PUB3, PUB7 to PUB9) (1) Port mode registers (PM0 to PM3, PM5, PM7 to PM9) These registers are used to set port input/output in 1-bit units. The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the registers to FFH. When port pins are used as alternate-function pins, set the port mode register and output latch according to Table 4-3. Caution As port 3 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be preset to 1. 96 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Format of Port Mode Register Symbol PM0 7 1 6 1 5 1 4 1 3 2 1 0 Address FF20H After reset FFH R/W R/W PM03 PM02 PM01 PM00 PM1 1 1 1 1 PM13 PM12 PM11 PM10 FF21H FFH R/W PM2 1 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W PM5 1 1 1 1 PM53 PM52 PM51 PM50 FF25H FFH R/W PM7 1 1 1 1 1 PM72 PM71 PM70 FF27H FFH R/W PM8Note 1 1 1 1 1 1 PM81 PM80 FF28H FFH R/W PM9Note PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 FF29H FFH R/W PMmn Pmn pin input/output mode selection (m = 0 to 3, 5, 7 to 9, n = 0 to 7) 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) Note Incorporated only in the PD789426 and 789436 Subseries. User's Manual U15075EJ1V0UM00 97 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Alternate Function Pin Name Name P00 to P03 P26 P30 KR0 to KR3 TO90 INTP0 CPT90 P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 INTP3 TO61 P60 to P65 ANI0 to ANI5 Input Output Input Input Input Output Input Input Output Input Output Input I/O 1 0 1 1 1 0 1 1 0 1 0 1 x 0 x x x 0 x x 0 x 0 x PMxx Pxx Caution When port 2 is used as a serial interface pin, the I/O latch or output latch must be set according to its function. For the setting method, see Table 12-2 Settings of Serial Interface 20 Operating Mode. Remark x: PMxx: Pxx: don't care Port mode register Port output latch (2) Pull-up resistor option register 0 (PU0) Pull-up resistor option register 0 (PU0) sets whether on-chip pull-up registers are used on ports 0 and 1 or not. On the port specified to use an on-chip pull-up resistor by PU0, the pull-up resistor can be internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PU0. This also applies to cases when the pins are used for alternate functions. PU0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PU0 to 00H. Figure 4-19. Format of Pull-Up Resistor Option Register 0 Symbol PU0 7 0 6 0 5 0 4 0 3 0 2 0 <1> <0> Address FFF7H After reset 00H R/W R/W PU01 PU00 PU0m Pm on-chip pull-up resistor selection (m = 0, 1) 0 1 On-chip pull-up resistor not used On-chip pull-up resistor used Caution Bits 2 to 7 must be set to 0. User's Manual U15075EJ1V0UM00 98 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option register B2 (PUB2) Pull-up resistor option register B2 (PUB2) sets whether on-chip pull-up resistors on P20 to P26 are used or not. On the port specified to use an on-chip pull-up resistor by PUB2, the pull-up resistor can be internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PUB2. This also applies to cases when the pins are used for alternate functions. PUB2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PUB2 to 00H. Figure 4-20. Format of Pull-Up Resistor Option Register B2 Symbol PUB2 7 0 <6> <5> <4> <3> <2> <1> <0> Address FF32H After reset 00H R/W R/W PUB26 PUB25 PUB24 PUB23 PUB22 PUB21 PUB20 PUB2n P2n on-chip pull-up resistor selection (n = 0 to 6) 0 1 On-chip pull-up resistor not used On-chip pull-up resistor used (4) Pull-up resistor option register B3 (PUB3) Pull-up resistor option register B3 (PUB3) sets whether on-chip pull-up resistors on P30 to P33 are used or not. On the port specified to use an on-chip pull-up resistor by PUB3, the pull-up resistor can be internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PUB3. This also applies to cases when the pins are used for alternate functions. PUB3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PUB3 to 00H. Figure 4-21. Format of Pull-Up Resistor Option Register B3 Symbol PUB3 7 0 6 0 5 0 4 0 <3> <2> <1> <0> Address FF33H After reset 00H R/W R/W PUB33 PUB32 PUB31 PUB30 PUB3n P3n on-chip pull-up resistor selection (n = 0 to 3) 0 1 On-chip pull-up resistor not used On-chip pull-up resistor used User's Manual U15075EJ1V0UM00 99 CHAPTER 4 PORT FUNCTIONS (5) Pull-up resistor option register B7 (PUB7) Pull-up resistor option register B7 (PUB7) sets whether on-chip pull-up resistors on P70 to P72 are used or not. On the port specified to use an on-chip pull-up resistor by PUB7, the pull-up resistor can be internally used only for bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PUB7. This also applies to when the pins are used for alternate function. PUB7 is set with a 1-bit or 8-bit memory manipulation instructions. RESET input sets PUB7 to 00H. Figure 4-22. Format of Pull-Up Resistor Option Register B7 Symbol PUB7 7 0 6 0 5 0 4 0 3 0 <2> <1> <0> Address FF37H After reset 00H R/W R/W PUB72 PUB71 PUB70 PUB7n P7n on-chip pull-up resistor selection (n = 0 to 2) 0 1 On-chip pull-up resistor not used On-chip pull-up resistor used (6) Pull-up resistor option register B8 (PUB8) Note Pull-up resistor option register B8 (PUB8) sets whether on-chip pull-up resistors on P80 and P81 are used or not. On the port specified to use an on-chip pull-up resistor by PUB8, the pull-up resistor can be internally used only for bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PUB8. This also applies to when the pins are used for alternate functions. PUB8 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PUB8 to 00H. Note Incorporated only in the PD789426 and 789436 Subseries. Figure 4-23. Format of Pull-Up Resistor Option Register B8 Symbol PUB8 7 0 6 0 5 0 4 0 3 0 2 0 <1> <0> Address FF38H After reset 00H R/W R/W PUB81 PUB80 PUB8n P8n on-chip pull-up resistor selection (n = 0, 1) 0 1 On-chip pull-up resistor not used On-chip pull-up resistor used 100 User's Manual U15075EJ1V0UM00 CHAPTER 4 PORT FUNCTIONS (7) Pull-up resistor option register B9 (PUB9) Note Pull-up resistor option register B9 (PUB9) sets whether on-chip pull-up resistors on P90 to P97 are used or not. On the port specified to use an on-chip pull-up resistor by PUB9, the pull-up resistor can be internally used only for bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PUB9. This also applies to when the pins are used for alternate function. PUB9 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PUB9 to 00H. Note Incorporated only in the PD789426 and 789436 Subseries. Figure 4-24. Format of Pull-Up Resistor Option Register B9 Symbol PUB9 <7> <6> <5> <4> <3> <2> <1> <0> Address FF39H After reset 00H R/W R/W PUB97 PUB96 PUB95 PUB94 PUB93 PUB92 PUB91 PUB90 PUB9n P9n on-chip pull-up resistor selection (n = 0 to 7) 0 1 On-chip pull-up resistor not used On-chip pull-up resistor used User's Manual U15075EJ1V0UM00 101 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. Data once written to the output latch is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF. Data once written to the output latch is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 Reading from I/O port (1) In output mode The status of an output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. 4.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed with the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. Data once written to the output latch is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 102 User's Manual U15075EJ1V0UM00 CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. * Main system clock oscillator This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). * Subsystem clock oscillator This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM). 5.2 Clock Generator Configuration The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Processor clock control register (PCC) Suboscillation mode register (SCKM) Subclock control register (CSS) Main system clock oscillator Subsystem clock oscillator Configuration Oscillators User's Manual U15075EJ1V0UM00 103 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus FRC SCC Suboscillation mode register (SCKM) XT1 XT2 Subsystem clock oscillator fXT Prescaler 1/2 fXT 2 16-bit timer 90 8-bit timer 60 Watch timer LCD controller/driver Clock to peripheral hardware X1 X2 fX 22 Selector Main system clock oscillator Prescaler fX Standby controller Wait controller CPU clock (fCPU) STOP MCC PCC1 Processor clock control register (PCC) Internal bus CLS CSS0 Subclock control register (CSS) 104 User's Manual U15075EJ1V0UM00 CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following registers. * Processor clock control register (PCC) * Suboscillation mode register (SCKM) * Subclock control register (CSS) (1) Processor clock control register (PCC) PCC sets CPU clock selection and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 5-2. Format of Processor Clock Control Register Symbol <7> PCC MCC 6 0 5 0 4 0 3 0 2 0 1 PCC1 0 0 Address FFFBH After reset 02H R/W R/W MCC 0 1 Operation enabled Operation disabled Control of main system clock oscillator operation CSS0 PCC1 0 0 1 1 0 1 0 1 fX (0.2 s) CPU clock (fCPU) selectionNote fX/22 (0.8 s) fXT/2 (61 s) Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to 5.3 (3) Subclock control register (CSS)). Cautions 1. Bits 0 and 2 to 6 must be set to 0. 2. The MCC can be set only when the subsystem clock has been selected as the CPU clock. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. 4. Minimum instruction execution time: 2fCPU * fCPU = 0.2 s: 0.4 s * fCPU = 0.8 s: 1.6 s * fCPU = 61 s: 122 s User's Manual U15075EJ1V0UM00 105 CHAPTER 5 CLOCK GENERATOR (2) Suboscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H. Figure 5-3. Format of Suboscillation Mode Register Symbol SCKM 7 0 6 0 5 0 4 0 3 0 2 0 1 FRC 0 SCC Address FFF0H After reset 00H R/W R/W FRC 0 1 On-chip feedback resistor used On-chip feedback resistor not used Feedback resistor selection SCC 0 1 Operation enabled Operation disabled Control of subsystem clock oscillator operation Caution Bits 2 to 7 must be set to 0. 106 User's Manual U15075EJ1V0UM00 CHAPTER 5 CLOCK GENERATOR (3) Subclock control register (CSS) CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the CPU clock operation status. CSS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSS to 00H. Figure 5-4. Format of Subclock Control Register Symbol CSS 7 0 6 0 5 4 3 0 2 0 1 0 0 0 Address FFF2H After reset 00H R/W R/WNote CLS CSS0 CLS 0 1 CPU clock operation status Operation based on the output of the (divided) main system clock Operation based on the subsystem clock CSS0 0 1 Selection of the main system or subsystem clock oscillator (Divided) output from the main system clock oscillator Output from the subsystem clock oscillator Note Bit 5 is read only. Caution Bits 0 to 3, 6, and 7 must be set to 0. User's Manual U15075EJ1V0UM00 107 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin. Figure 5-5 shows the external circuit of the main system clock oscillator. Figure 5-5. External Circuit of Main System Clock Oscillator (a) Crystal or ceramic oscillation VSS X1 External clock (b) External clock X1 X2 Crystal or ceramic resonator X2 108 User's Manual U15075EJ1V0UM00 CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin. Figure 5-6 shows the external circuit of the subsystem clock oscillator. Figure 5-6. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation VSS XT1 32.768 kHz XT2 Crystal resonator External clock (b) External clock XT1 XT2 Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. When using the subsystem clock, particular care is required because the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption. Figure 5-7 shows examples of incorrect resonator connection. User's Manual U15075EJ1V0UM00 109 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 3, 5) VSS X1 X2 VSS X1 X2 (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 VSS X1 X2 High current A B High current C Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. 110 User's Manual U15075EJ1V0UM00 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched (f) Parallel and near signal lines of main system clock and subsystem clock VSS X2 X1 XT2 XT1 VSS X1 X2 XT2 is wired parallel to X1. Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. Caution If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between the X1 and XT2, resulting in a malfunction. To avoid this, do not lay the X1 and XT2 wires in parallel. 5.4.3 Divider circuit The divider circuit divides the output of the main system clock oscillator (fX) to generate various clocks. 5.4.4 When no subsystem clock is used If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the XT1 and XT2 pins as follows: XT1: Connect to VSS XT2: Leave open In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above. User's Manual U15075EJ1V0UM00 111 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. * Main system clock * Subsystem clock * CPU clock fCPU fX fXT * Clock to peripheral hardware The operation and function of the clock generator is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows. (a) The low-speed mode 2fCPU (1.6 s: at 5.0 MHz operation) of the main system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the main system clock is stopped. (b) Three types of CPU clocks fCPU (0.2 s and 0.8 s: main system clock (at 5.0 MHz operation), 61 s: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and CSS settings. (c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system where no subsystem clock is used, setting bit 1 (FRC) of the SCKM so that the on-chip feedback resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation. (d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation is used (122 s: at 32.768 kHz operation). (e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot. (f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system clock, but the subsystem clock pulse is only supplied to the 16-bit timer, 8-bit timer, watch timer, and LCD controller/driver. The 16-bit timer, 8-bit timer, watch timer, and LCD controller/driver can therefore keep running even during standby. The other hardware stops when the main system clock stops because it runs based on the main system clock (except for external input clock operations). 112 User's Manual U15075EJ1V0UM00 CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 5-2). Table 5-2. Maximum Time Required for Switching CPU Clock Set Value Before Switching CSS0 PCC1 CSS0 0 0 0 PCC1 0 Set Value After Switching CSS0 0 4 clocks PCC1 1 CSS0 1 2fX/fXT clocks (306 clocks) fX/2fXT clocks (76 clocks) 2 clocks PCC1 x 1 2 clocks 1 x 2 clocks Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching. 2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. 3. x: don't care User's Manual U15075EJ1V0UM00 113 CHAPTER 5 CLOCK GENERATOR 5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-8. Switching Between System Clock and CPU Clock VDD RESET Interrupt request signal System clock CPU clock fX Low-speed operation fX High-speed operation fXT Subsystem clock operation fX High-speed operation Wait (6.55 ms: at 5.0 MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the oscillation stabilization time (215/fX) is automatically secured. After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6 s: at 5.0 MHz operation). <2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS) are rewritten so that high-speed operation can be selected. <3> A drop of the VDD voltage is detected with an interrupt request signal. The clock is switched to the subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status). <4> A recover of the VDD voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and then the main system clock starts oscillating. After the time required for the oscillation to stabilize has elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again. Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 114 User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER 6.1 16-Bit Timer Functions The 16-bit timer has the following functions. * Timer interrupt * Timer output * Buzzer output * Count value capture (1) Timer interrupt An interrupt is generated when a count value and compare value matches. (2) Timer output Timer output can be controlled when a count value and compare value matches. (3) Buzzer output Buzzer output can be controlled by software. (4) Count value capture A count value of 16-bit timer counter 90 (TM90) is latched into a capture register synchronizing with the capture trigger and retained. User's Manual U15075EJ1V0UM00 115 CHAPTER 6 16-BIT TIMER 6.2 16-Bit Timer Configuration The 16-bit timer includes the following hardware. Table 6-1. 16-Bit Timer Configuration Item Timer counters Registers 16 bits x 1 (TM90) Compare register: Capture register: 1 (TO90) 16-bit timer mode control register 90 (TMC90) Buzzer output control register 90 (BZC90) Port mode register 2 (PM2) 16 bits x 1 (CR90) 16 bits x 1 (TCP90) Configuration Timer outputs Control registers 116 User's Manual U15075EJ1V0UM00 Figure 6-1. Block Diagram of 16-Bit Timer Internal bus 16-bit timer mode control register 90 (TMC90) TOF90 CPT901 CPT900 TOC90 TCL901TCL900 TOE90 P26 Output latch PM26 16-bit compare register 90 (CR90) Selector TO90/P26 F/F TOD90 Selector User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER fX fXT fX/22 fX/26 fX/27 Match INTTM90 Selector Synchronization circuit OVF 16-bit timer counter 90 (TM90) BZO90/P21 CTP90/INTP0 /TI81/P30 Edge detector 16-bit capture register 90 (TCP90) 16-bit counter read buffer 3 P21 Output latch PM21 BCS902 BCS901 BCS900 BZOE90 Write controller fX/2 Write controller CPU clock Internal bus Buzzer output control register (BZC90) 117 CHAPTER 6 16-BIT TIMER (1) 16-bit compare register 90 (CR90) A value specified in CR90 is compared with the count in 16-bit timer register 90 (TM90). If they match, an interrupt request (INTTM90) is issued by CR90. CR90 is set with an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH can be set. RESET input sets CR90 to FFFFH. Cautions 1. CR90 is designed to be manipulated with a 16-bit memory manipulation instruction. However, it can also be manipulated with an 8-bit memory manipulation instruction. When an 8-bit memory manipulation instruction is used to set CR90, it must be accessed by direct addressing. 2. To overwrite CR90 during a count operation, it is necessary to disable interrupts in advance, using interrupt mask flag register 1 (MK1). It is also necessary to disable inversion of the timer output data, using 16-bit timer mode control register 90 (TMC90). If the value in CR90 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 90 (TM90) TM90 is used to count the number of pulses. The contents of TM90 are read with an 8-bit or 16-bit memory manipulation instruction. RESET input sets TM90 to 0000H. Cautions 1. The count becomes undefined when STOP mode is deselected, because the count operation is performed before oscillation stabilizes. 2. TM90 is designed to be manipulated with a 16-bit memory manipulation instruction. However, it can also be manipulated with an 8-bit memory manipulation instruction. When an 8-bit memory instruction is used to manipulate TM90, it must be accessed by direct addressing. 3. When an 8-bit memory manipulation instruction is used to manipulate TM90, the lower and higher bytes must be read as a pair, in this order. (3) 16-bit capture register 90 (TCP90) TCP90 captures the contents of TM90. It is set with an 8-bit or 16-bit memory manipulation instruction. RESET input makes TCP90 undefined. Caution TCP90 is designed to be manipulated with a 16-bit memory manipulation instruction. However, it can also be manipulated with an 8-bit memory manipulation instruction. When an 8-bit memory manipulation instruction is used to manipulate TCP90, it must be accessed by direct addressing. (4) 16-bit counter read buffer 90 This buffer is used to latch and hold the count value for TM90. 118 User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER 6.3 Registers Controlling 16-Bit Timer The 16-bit timer is controlled by the following three registers. * 16-bit timer mode control register 90 (TMC90) * Buzzer output control register 90 (BZC90) * Port mode register 2 (PM2) (1) 16-bit timer mode control register 90 (TMC90) 16-bit timer mode control register 90 (TMC90) controls the setting of a count clock, capture edge, etc. TMC90 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC90 to 00H. User's Manual U15075EJ1V0UM00 119 CHAPTER 6 16-BIT TIMER Figure 6-2. Format of 16-Bit Timer Mode Control Register 90 Symbol <7> <6> 5 4 3 2 1 <0> Address FF48H After reset 00H R/W R/WNote TMC90 TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TOD90 0 1 Timer output data is "0" Timer output data is "1" Timer output data TOF90 0 1 Reset or cleared by software Set when the 16-bit timer overflows Overflow flag control CPT901 CPT900 Capture edge selection Capture operation disabled Captured at the rising edge of the CPT90 pin Captured at the falling edge of the CPT90 pin Captured at both the rising and falling edges of the CPT90 pin 0 0 1 1 0 1 0 1 TOC90 0 1 Inversion disabled Inversion enabled Timer output data inversion control TCL901 TCL900 16-bit timer counter 90 count clock selection fX/2 (1.25 MHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fXT (32.768 kHz) 2 0 0 1 1 0 1 0 1 TOE90 0 1 Output disabled (port mode) Output enabled 16-bit timer counter 90 output control Note Bit 7 is read-only. Caution Disable interrupts in advance by using the interrupt mask flag register (MK1) to change the data of TCL901 and TCL900. Also, prevent the timer output data from being inverted by setting TOC90 to1. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. 120 User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER (2) Buzzer output control register 90 (BZC90) This register selects a buzzer frequency based on fcl selected with the count clock select bits (TCL901 and TCL900), and controls the output of the square wave. BZC90 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets BZC90 to 00H. Figure 6-3. Format of Buzzer Output Control Register 90 Symbol BZC90 7 0 6 0 5 0 4 0 3 BCS902 2 BCS901 1 <0> Address FF49H After reset 00H R/W R/W Note BCS900 BZOE90 BCS902 BCS901 BCS900 fcl = fX/2 2 4 5 Buzzer frequency fcl = fX/26 fcl/2 (4.88 kHz) fcl/2 (2.44 kHz) fcl/28 (305 Hz) fcl/29 (153 Hz) fcl/210 (76 Hz) fcl/211 (38 Hz) fcl/212 (19 Hz) fcl/213 (10 Hz) 4 5 fcl = fX/27 fcl/2 (2.44 kHz) fcl/2 (1.22 kHz) fcl/28 (153 Hz) fcl/29 (76 Hz) fcl/210 (38 Hz) fcl/211 (19 Hz) fcl/212 (10 Hz) fcl/213 (5 Hz) 4 fcl = fXT fcl/2 (2.05 kHz) fcl/25 (1.02 kHz) fcl/28 (128 Hz) fcl/29 (64 Hz) fcl/210 (32 Hz) fcl/211 (16 Hz) fcl/212 (8 Hz) fcl/213 (4 Hz) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fcl/2 (78.1 kHz) 4 5 fcl/2 (39.1 kHz) fcl/28 (4.88 kHz) fcl/29 (2.44 kHz) fcl/210 (1.22 kHz) fcl/211 (610 Hz) fcl/212 (305 Hz) fcl/213 (153 Hz) BZOE90 0 1 Disables buzzer port output. Enables buzzer port output. Buzzer port output control Note Bits 4 to 7 must be set to 0. Caution If the subclock is selected as the count clock (TCL901 = 1, TCL900 = 1: see Figure 6-2 Format of 16-Bit Timer Mode Control Register 90), the subclock is not synchronized when buzzer port output is enabled. In this case, the capture function and TM90 read function are disabled. In addition, the count value of TM90 is undefined. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. User's Manual U15075EJ1V0UM00 121 CHAPTER 6 16-BIT TIMER (3) Port mode register 2 (PM2) PM2 is used to set each bit of port 3 to input or output. When pin P26/ITO90 is used for timer output, reset the output latch of P26 and PM26 to 0; when pin P21/BZO90 is used for buzzer output, reset the output latch of P26 and PM26 to 0. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 6-4. Format of Port Mode Register 2 Symbol PM2 7 1 6 PM26 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20 Address FF22H After reset FFH R/W R/W PM2n 0 1 Output mode (output buffer ON) Input mode (output buffer OFF) P2n pin I/O mode (n =1, 6) 122 User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER 6.4 16-Bit Timer Operation 6.4.1 Operation as timer interrupt In the timer interrupt function, interrupts are repeatedly generated at the count value preset in 16-bit compare register 90 (CR90) based on the intervals of the value set in TCL901 and TCL900. To operate the 16-bit timer as a timer interrupt, the following settings are required. * Set count values in CR90 * Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-5. Figure 6-5. Settings of 16-Bit Timer Mode Control Register 90 for Timer Interrupt Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 - 0/1 0/1 0/1 0/1 0 0/1 0/1 Setting of count clock (see Table 6-2) Caution If both the CPT901 and CPT900 flags are set to 0, the capture operation is prohibited. When the count value of 16-bit timer counter 90 (TM90) matches the value set in CR90, counting of TM90 continues and an interrupt request signal (INTTM90) is generated. Table 6-2 shows interval time, and Figure 6-6 shows timing of timer interrupt operation. Caution When rewriting the value in CR90 during a count operation, be sure to execute the following processing. <1> Set interrupt disabled (set TMMK90 (bit 4 of interrupt mask flag register 1 (MK1)) to 1). <2> Disable inversion control of timer output data (set TOC90 to 0) If the value in CR90 is rewritten in the interrupt-enabled state, an interrupt request may occur at the moment of rewrite. Table 6-2. Interval Time of 16-Bit Timer TCL901 0 0 1 1 TCL900 0 1 0 1 2 /fX (0.8 s) 2 Count Clock 2 /fX (52.4 ms) 2 /fX (838.9 ms) 2 /fX (1.68 s) 2 /fXT (2.0 s) 16 23 22 18 Interval Time 2 /fX (12.8 s) 6 2 /fX (25.6 s) 7 1/fXT (30.5 s) Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. User's Manual U15075EJ1V0UM00 123 CHAPTER 6 16-BIT TIMER Figure 6-6. Timing of Timer Interrupt Operation t Count clock TM90 count value CR90 INTTM90 Interrupt acknowledgement TO90 TOF90 Overflow flag set Interrupt acknowledgement 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N Remark N = 0000H to FFFFH 124 User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER 6.4.2 Operation as timer output Timer outputs are repeatedly generated at the count value preset in 16-bit compare register 90 (CR90) based on the intervals of the value set in TCL901 and TCL900. To operate the 16-bit timer as a timer output, the following settings are required. * Set P26 to output mode (PM26 = 0). * Reset output latch of P26 to 0. * Set the count value in CR90. * Set 16-bit timer mode control register 90 (TMC90) as shown in Figure 6-7. Figure 6-7. Settings of 16-Bit Timer Mode Control Register 90 for Timer Output Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 - 0/1 0/1 0/1 1 0 0/1 1 TO90 output enable Setting of count clock (see Table 6-2) Inverse enable of timer output data Caution If both the CPT901 flag and CPT900 flag are set to 0, the capture operation is prohibited. When the count value of 16-bit timer counter 90 (TM90) matches the value set in CR90, the output status of the TO90/P26 pin is inverted. This enables timer output. At that time, TM90 counting continues and an interrupt request signal (INTTM90) is generated. Figure 6-8 shows the timing of timer output (see Table 6-2 for the interval time of the 16-bit timer). Figure 6-8. Timer Output Timing t Count clock TM90 count value CR90 INTTM90 Interrupt acknowledgement TO90Note TOF90 Overflow flag set Interrupt acknowledgement 0000H N 0001H N N FFFFH 0000H 0001H N N N FFFFH N Note The initial value of TO90 becomes low level when output is enabled (TOE90 = 1). Remark N = 0000H to FFFFH User's Manual U15075EJ1V0UM00 125 CHAPTER 6 16-BIT TIMER 6.4.3 Capture operation The capture operation consists of latching the count value of 16-bit timer register 90 (TM90) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC90 as shown in Figure 6-9 to allow the 16-bit timer to start the capture operation. Figure 6-9. Settings of 16-Bit Timer Mode Control Register 90 for Capture Operation TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TMC90 - 0/1 0/1 0/1 0/1 0 0/1 0/1 Count clock selection Capture edge selection (see Table 6-3) 16-bit capture register 90 (TCP90) starts a capture operation after a CPT90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer register 90. The TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection. Table 6-3 and Figure 6-10 show the settings of the capture edge and the capture operation timing, respectively. Table 6-3. Settings of Capture Edge CPT901 0 0 1 1 CPT900 0 1 0 1 Capture operation prohibited CPT90 pin rising edge CPT90 pin falling edge CPT90 pin both edges Capture Edge Selection Caution Because TCP90 is rewritten when a capture trigger edge is detected during TCP90 read, disable the capture trigger edge detection during TCP90 read. Figure 6-10. Capture Operation Timing (Both Edges of CPT90 Pin Are Specified) Count clock TM90 Count read buffer TCP90 0000H 0000H 0001H 0001H Undefined Capture start CPT90 Capture edge detection Capture edge detection N N N M 1 M M M Capture start 126 User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER 6.4.4 16-bit timer counter 90 readout The count value of 16-bit timer counter 90 (TM90) is read out using a 16-bit manipulation instruction. TM90 readout is performed through a counter read buffer. The counter read buffer latches the TM90 count value, and the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM90 lower byte rises, and the count value is retained. The retained counter read buffer value can be read out as the count value. Cancellation of the pending state is performed at the CPU clock falling edge after the read signal of the TM90 higher byte falls. RESET input sets TM90 to 0000H and TM90 starts freerunning. Figure 6-11 shows the timing of 16-bit timer counter 90 readout. Cautions 1. The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time. 2. Though TM90 is designed for a 16-bit transfer instruction, an 8-bit transfer instruction can also be used. When using an 8-bit transfer instruction, execute it by direct addressing. 3. When using an 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. If only the lower byte is read, the pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined count value is read. Figure 6-11. 16-Bit Timer Counter 90 Readout Timing CPU clock Count clock TM90 Count read buffer TM90 read signal Read signal latch prohibited period 0000H 0000H 0001H 0001H N N N+1 User's Manual U15075EJ1V0UM00 127 CHAPTER 6 16-BIT TIMER 6.4.5 Buzzer output operation The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output. Table 6-4 shows the buzzer frequency. Set the 16-bit timer as follows to use it for buzzer output: * Set P21 to output mode (PM21 = 0). * Reset output latch of P21 to 0. * Set a count clock using TCL901 and TCL900. * Set BZC90 as shown in Figure 6-12. Figure 6-12. Settings of Buzzer Output Control Register 90 for Buzzer Output Operation BCS902 BCS901 BCS900 BZOE90 BZC90 0 0 0 0 0/1 0/1 0/1 1 Enables buzzer output Setting of buzzer frequency (see Table 6-4) Table 6-4. Buzzer Frequency of 16-Bit Timer BCS902 BCS901 BCS900 fcl = fX/2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 4 2 Buzzer Frequency fcl = fX/2 4 6 fcl = fX/2 4 7 fcl = fXT fcl/2 (2.05 kHz) fcl/2 (1.02 kHz) fcl/2 (128 Hz) fcl/2 (64 Hz) fcl/2 (32 Hz) fcl/2 (16 Hz) fcl/2 (8 Hz) fcl/2 (4 Hz) 13 12 11 10 9 8 5 4 fcl/2 (78.1 kHz) fcl/2 (39.1 kHz) fcl/2 (4.88 kHz) fcl/2 (2.44 kHz) fcl/2 (1.22 kHz) fcl/2 (610 Hz) fcl/2 (305 Hz) fcl/2 (153 Hz) 13 12 11 10 9 8 5 fcl/2 (4.88 kHz) fcl/2 (2.44 kHz) fcl/2 (305 Hz) fcl/2 (153 Hz) fcl/2 (76 Hz) fcl/2 (38 Hz) fcl/2 (19 Hz) fcl/2 (10 Hz) 13 12 11 10 9 8 5 fcl/2 (2.44 kHz) fcl/2 (1.22 kHz) fcl/2 (153 Hz) fcl/2 (76 Hz) fcl/2 (38 Hz) fcl/2 (19 Hz) fcl/2 (10 Hz) fcl/2 (5 Hz) 13 12 11 10 9 8 5 Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. 128 User's Manual U15075EJ1V0UM00 CHAPTER 6 16-BIT TIMER 6.5 Notes on Using 16-Bit Timer Usable functions differ according to the settings of the count clock selection, CPU clock operation, system clock oscillation status, and BZOE90 (bit 0 of buzzer output control register 90 (BZC90)). Refer to the following table. Count Clock fX/2 , 6 fX/2 , 7 fX/2 2 CPU Clock Main System Clock Main System Clock Subsystem Clock Oscillating Stopped Oscillating/Stopped BZOE90 Capture TM90 Read Note 1 x x x x x x x x x x x Buzzer Output Note 2 x Note 2 x x x x x x x Timer Output x x x x x x Timer Interrupt x x x x x x 1/0 x Sub Oscillating Stopped Oscillating x fXT Main Oscillating Oscillating 0 1 x x x x x x x x Stopped Stopped (STOP mode) Oscillating 1/0 0 1 Stopped Sub Oscillating Oscillating 1/0 0 1 Stopped 0 1 Notes 1. TM90 is enabled only when the CPU clock is in high-speed mode. 2. Output is enabled when BZOE90 = 1. Cautions 1. The capture function uses fX/2 for control (refer to Figure 6-1 Block Diagram of 16-Bit Timer). Therefore, the capture function cannot be used when the main system clock is stopped. 2. The read function of TM90 uses the CPU clock for control (refer to Figure 6-1), and reads an undefined value when the CPU clock is slower than the count clock (values are not guaranteed). When reading TM90, set the count clock to the same speed as the CPU clock (when the CPU clock is the main system clock, high-speed mode is set), or select a clock slower than the CPU clock. 3. When the subsystem clock is selected as the count clock and BZOE90 is set to 0, the subsystem clock selected as the TM90 count clock is one that has been synchronized with the main system clock (refer to Figure 6-1). Therefore, when the main system clock oscillation is stopped, the timer operation is stopped because the clock supplied to the 16bit timer is stopped (timer interrupt is not generated). Moreover, when the subsystem clock is selected as the count clock and BZOE90 is set to 1, the capture and TM90 read values are not guaranteed because the subsystem clock is not synchronized. Therefore, be sure to set BZOE90 to 0 when using the capture and TM90 read functions (when the subsystem clock is selected as the count clock, buzzer output, capture, and TM90 read functions cannot be used at the same time). User's Manual U15075EJ1V0UM00 129 CHAPTER 6 16-BIT TIMER Make the following settings when stopping the main system clock oscillation to support low current consumption and releasing the HALT mode. Count clock: CPU clock: Main system clock: BZOE90: Subsystem clock Subsystem clock Oscillation stopped 1 (Buzzer output enabled) At this time, when the setting of P21, the buzzer output alternate function pin, is "PM21 = 0, P21 = 0", a square wave of the buzzer frequency is output from P21. To avoid outputting the buzzer frequency, make either of the following settings. * * Set P21 to input mode (PM21 = 1) If P21 cannot be set to input mode, set the port latch value of P21 to 1 (P21 = 1) (In this case, a high level is output from P21) 130 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER 7.1 8-Bit Timer Functions An 8-bit timer (one channel, timer 50) and an 8-bit timer/event counter (one channel, timer 60) are incorporated in the PD789426, 789436, 799446, 789456 Subseries. The operation modes listed in the following table can be set via mode register settings. Table 7-1. Operation Modes Channel Mode 8-bit timer counter mode (Discrete mode) 16-bit timer counter mode (Cascade connection mode) Carrier generator mode PWM output mode Available Available Timer 50 Timer 60 Available Available Available (Free-running mode) Available (Pulse generator mode) (1) 8-bit timer counter mode (discrete mode) The following functions can be used in this mode. * Interval timer with 8-bit resolution * External event counter with 8-bit resolution (timer 40 only) * Square wave output with 8-bit resolution (2) 16-bit timer counter mode (cascade connection mode) Operation as a 16-bit timer/event counter is enabled during cascade connection mode. The following functions can be used in this mode. * Interval timer with 16-bit resolution * External event counter with 16-bit resolution * Square wave output with 16-bit resolution (3) Carrier generator mode The carrier clock generated by timer 60 is output in cycles set by timer 50. (4) PWM output mode (a) Timer 50: Free-running mode The timer output status inverts repeatedly due to a match between TM50 and CR50 and TM50 overflow, and pulses of any duty ratio are output. User's Manual U15075EJ1V0UM00 131 CHAPTER 7 8-BIT TIMER (b) Timer 60: Pulse generator mode The timer output status inverts repeatedly due to the settings of TM60, CR60, and CRH60, and pulses of any duty ratio are output (either P32/INTP2/TO60 or P33/INTP3/TO61 can be selected as the timer output pin using software). 7.2 8-Bit Timer Configuration The 8-bit timer includes the following hardware. Table 7-2. 8-Bit Timer Configuration Item Timer counters Registers Timer outputs Control registers 8 bits x 2 (TM50, TM60) Compare registers: 8 bits x 3 (CR50, CR60, CRH60) 3 (TO50, TO60, TO61) 8-bit timer mode control register 50 (TMC50) 8-bit timer mode control register 60 (TMC60) Carrier generator output control register 60 (TCA60) Port mode register 3 (PM3) Configuration 132 User's Manual U15075EJ1V0UM00 Figure 7-1. Block Diagram of Timer 50 Internal bus 8-bit timer mode control register 50 (TMC50) TCE50 TEG50 TCL502 TCL501 TCL500 TMD501 TMD500 TOE50 P31 output latch PM31 Decoder 8-bit compare register 50 (CR50) Match To Figure 7-2 (F) Timer 50 match signal (in cascade connection mode) INTTM50 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Bit 7 of TM60 (from Figure 7-2 (A)) fX fX/23 fX/27 fXT Timer 60 interrupt request signal (from Figure 7-2 (B)) Carrier clock (in carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) (from Figure 7-2 (C)) Selector Selector 8-bit timer counter 50 (TM50) Clear Selector OVF IN S Q CK Q R TO50/TMI60/INTP1/P31 To Figure 7-2 (G) Timer 50 match signal (in carrier generator mode) Cascade connection mode PWM mode From Figure 7-2 (E) Timer 60 match signal (in cascade connection mode) From Figure 7-2 (D) Count operation start signal (in cascade connection mode) 133 Prescaler fTMI/2 fTMI/22 fTMI/2 3 Selector 134 Figure 7-2. Block Diagram of Timer 60 Internal bus 8-bit timer mode control register 60 (TMC60) TCE60 TCL602 TCL601 TCL600 TMD601 TMD600 TOE60 8-bit compare register H60 (CRH60) 8-bit compare register 60 (CR60) Carrier generator output control register 60 (TCA60) RMC60 NRZB60 NRZ60 Decoder Selector From Figure 7-1 (G) Timer counter match signal from timer 50 (in carrier generator mode) Match fX fX/22 fTMI F/F TO60/INTP2/P32 Output control lerNote User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER TO61/INTP3/P33 To Figure 7-1 (C) Carrier clock (during carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) 8-bit timer counter 60 (TM60) OVF Clear PWM mode Reset Cascade connection mode TMI60/TO50 /INTP1/P31 To Figure 7-1 (A) Bit 7 of TM60 (in cascade connection mode) To Figure 7-1 (D) Count operation start signal to timer 50 (in cascade connection mode) To Figure 7-1 (E) TM60 timer counter match signal (in cascade connection mode) INTTM60 To Figure 7-1 (B) Timer 60 interrupt request signal count clock input signal to TM50 From Figure 7-1 (F) TM50 match signal (in cascade connection mode) Note For details, see Figure 7-3. CHAPTER 7 8-BIT TIMER Figure 7-3. Block Diagram of Output Controller (Timer 60) TOE60 TOE61 P33 P32 Output latch Output latch PM32 PM33 F/F TO60/P32/ INTP2 TO61/P33/ INTP3 Timer 60 output signal (1) 8-bit compare register 50 (CR50) This 8-bit register is used to continually compare the value set to CR50 with the count value in 8-bit timer counter 50 (TM50) and to generate an interrupt request (INTTM50) when a match occurs. CR50 is set with an 8-bit memory manipulation instruction. RESET input makes CR50 undefined. Cautions 1. If the CR50 is overwritten during timer operation in the PWM output mode (TMD501 = 1, TMD500 = 0), a high level may be output for 1 cycle immediately after. If this waveform poses a problem for the application, either <1> stop the timer when overwriting the CR50, or <2> overwrite the CR50 with the TOE50 in a cleared status. 2. If the valid edge of the count clock is selected for both edges in the PWM output mode (TEG50 = 1), do not set 00H, 01H, and FFH to the CR50. If the rising edge is selected (TEG50 = 0), do not set 00H to CR50. (2) 8-bit compare register 60 (CR60) This 8-bit register is used to continually compare the value set to CR60 with the count value in 8-bit timer counter 60 (TM60) and to generate an interrupt request (INTTM60) when a match occurs. When connected to TM50 via a cascade connection and used as a 16-bit timer/event counter, the interrupt request (INTTM60) occurs only when matches occur simultaneously between CR50 and TM50 and between CR60 and TM60 (INTTM50 does not occur). CR60 is set with an 8-bit memory manipulation instruction. RESET input makes CR60 undefined. (3) 8-bit compare register H60 (CRH60) In PWM output mode, the high-level width of timer output is set by writing a value to CRH60. CRH60 is set with an 8-bit memory manipulation instruction. RESET input makes CRH60 undefined. User's Manual U15075EJ1V0UM00 135 CHAPTER 7 8-BIT TIMER (4) 8-bit timer counters 50 and 60 (TM50 and TM60) These are 8-bit registers that are used to count the count pulse. TM50 and TM60 are read with an 8-bit memory manipulation instruction. RESET input sets TM50 and TM60 to 00H. TM50 and TM60 are cleared to 00H under the following conditions. (a) Discrete mode (i) TM50 * After reset * When TCE50 (bit 7 of 8-bit timer mode control register 50 (TMC50)) is cleared to 0 * When a match occurs between TM50 and CR50 * When the TM50 count value overflows (ii) TM60 * After reset * When TCE60 (bit 7 of 8-bit timer mode control register 60 (TMC60)) is cleared to 0 * When a match occurs between TM60 and CR60 * When the TM60 count value overflows (b) Cascade connection mode (TM50 and TM60 are simultaneously cleared to 00H) * After reset * When the TCE60 flag is cleared to 0 * When matches occur simultaneously between TM50 and CR50 and between TM60 and CR60 * When the TM50 and TM60 count values overflow simultaneously (c) Carrier generator mode (i) TM50 * After reset * When the TCE50 flag is cleared to 0 * When a match occurs between TM50 and CR50 (ii) TM60 * After reset * When the TCE60 flag is cleared to 0 * When a match occurs between TM60 and CR60 * When a match occurs between TM60 and CRH60 136 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER (d) PWM output mode (i) TM50 * After reset * When the TCE50 flag is cleared to 0 * When a match occurs between TM50 and CR50 * When the TM50 count value overflows (ii) TM60 * Reset * When the TCE60 flag is cleared to 0 * When a match occurs between TM60 and CRH60 * When the TM60 count value overflows User's Manual U15075EJ1V0UM00 137 CHAPTER 7 8-BIT TIMER 7.3 Registers Controlling 8-Bit Timer The 8-bit timer is controlled by the following four registers. * 8-bit timer mode control register 50 (TMC50) * 8-bit timer mode control register 60 (TMC60) * Carrier generator output control register 60 (TCA60) * Port mode register 3 (PM3) (1) 8-bit timer mode control register 50 (TMC50) 8-bit timer mode control register 50 (TMC50) is used to control the timer 50 count clock setting and the operation mode setting. TMC50 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC50 to 00H. 138 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-4. Format of 8-Bit Timer Mode Control Register 50 Symbol TMC50 <7> TCE50 <6> TEG50 5 TCL502 4 TCL501 3 TCL500 2 TMD501 1 TMD500 <0> TOE50 Address FF4DH After reset 00H R/W R/W TCE50 0 1 Control of TM50 count operation Clears TM50 count value and stops operation Starts count operation Note 1 TEG50 0 1 Valid edge selection for TM50 count clock Counts at the rising edge of the count clock Counts at both edges of the count clock Note 2 TCL502 0 0 0 0 1 1 TCL501 0 0 1 1 0 0 TCL500 0 1 0 1 0 1 fX (5.0 MHz) fX/2 (625 kHz) fX/2 (39.1 kHz) fXT (32.768 kHz) Timer 60 match signal 7 3 Selection of timer 50 count clock Carrier clock (in carrier generator mode) or timer 60 output signal (in a mode other than carrier generator mode) Setting prohibited Other than above TMD501 0 0 0 1 TMD500 0 1 0 0 TMD601 0 0 1 1 TMD600 0 1 1 0 Selection of operation mode for timer 50 and timer 60 Discrete mode (8-bit timer counter mode) Cascade connection mode (16-bit timer counter mode) Carrier generator mode Timer 50: PWM free-running mode Timer 60: PWM pulse generator mode Setting prohibited Note 2 Other than above TOE50 0 1 Output disabled Output enabled Control of timer output Notes 1. 2. 3. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode, any setting for TCE30 is ignored. The selection of both edges is valid only in the PWM output mode. In 8-bit counter mode or cascade connection mode, counting is done using the rising edge even if TEG50 is set to "1". The operation mode selection is set to both the TMC30 register and TMC40 register. User's Manual U15075EJ1V0UM00 139 CHAPTER 7 8-BIT TIMER Cautions 1. In cascade connection mode, the output signal of timer 60 is forcibly selected as the count clock. 2. When operating TMC50, be sure to perform settings in the following order. <1> Stop TM50 count operation. <2> Set the operation mode and the count clock. <3> Start count operation. Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: Main system clock oscillation frequency (RC oscillation) (2) 8-bit timer mode control register 60 (TMC60) 8-bit timer mode control register 60 (TMC60) is used to control the timer 60 count clock setting and the operation mode setting. TMC60 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC60 to 00H. 140 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-5. Format of 8-Bit Timer Mode Control Register 60 Symbol TMC60 <7> TCE60 <6> TOE61 5 TCL602 4 TCL601 3 TCL600 2 TMD601 1 TMD600 <0> TOE60 Address FF4EH After reset 00H R/W R/W TCE60 0 1 Control of TM60 count operation Note 1 Clears TM60 count value and stops operation (the count value is also cleared for TM50 in cascade connection mode) Starts count operation (the count operation is also started for TM50 in cascade connection mode) TCL602 0 0 0 0 1 1 TCL601 0 0 1 1 0 0 TCL600 0 1 0 1 0 1 fX (5.0 MHz) fX/2 (1.25 MHz) fTMI (external input clock) fTMI/2 (external input clock) 2 Selection of timer 60 count clock fTMI/2 (external input clock) fTMI/2 (external input clock) Setting prohibited 3 2 Other than above TMD501 0 0 0 1 TMD500 0 1 0 0 TMD601 0 0 1 1 TMD600 0 1 1 0 Selection of operation mode for timer 50 and timer 60 Discrete mode (8-bit timer counter mode) Cascade connection mode (16-bit timer counter mode) Carrier generator mode Timer 50: PWM free-running mode Timer 60: PWM pulse generator mode Setting prohibited Note 2 Other than above TOE61 0 0 1 1 TOE60 0 1 0 1 Output disabled Output enabled only for TO60 Output enabled only for TO61 Setting prohibited Control of timer output Notes 1. 2. Since the count operation is controlled by TCE60 (bit 7 of TMC60) in cascade connection mode, any setting for TCE50 is ignored. The operation mode selection is set to both the TMC50 register and TMC60 register. Caution When operating the TMC60, be sure to perform settings in the following order. <1> Stop the TM60 count operation. <2> Set the operation mode and the count clock. <3> Start count operation. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U15075EJ1V0UM00 141 CHAPTER 7 8-BIT TIMER (3) Carrier generator output control register 60 (TCA60) This register is used to set the timer output data in carrier generator mode. TCA60 is set with an 8-bit memory manipulation instruction. RESET input sets TCA60 to 00H. Figure 7-6. Format of Carrier Generator Output Control Register 60 Symbol TCA60 7 0 6 0 5 0 4 0 3 0 <2> RMC60 <1> NRZB60 <0> NRZ60 Address FF4FH After reset 00H R/W W RMC60 0 Control of remote control output When NRZB60 = 1, a carrier pulse is output. When NRZB60 = 0, a low level is output. When NRZB60 = 1, high-level signal is output. When NRZB60 = 0, a low level is output. 1 NRZB60 This is the bit that stores the next data to be output to NRZ60. When a match signal occurs (for a match with timer 50), the data is output to NRZ60. Input the required value to NRZ60 by program beforehand. NRZ60 0 1 No return zero data Outputs low-level signal (carrier clock is stopped) Outputs carrier pulse Caution TCA60 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit memory manipulation instruction to set TCA60. (4) Port mode register 3 (PM3) This register is used to set the I/O mode of port 3 in 1-bit units. When using the P31/TO50/INTP1/TMI60 pin as a timer output, set the PM31 and P31 output latch to 0. When using the P32/TO60/INTP2 pin as a timer output, set the PM32 and P32 output latch to 0. When using the P33/TO61/INTP3 pin as a timer output, set the PM33 and P33 output latch to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 7-7. Format of Port Mode Register 3 Symbol PM3 7 1 6 1 5 1 4 1 3 PM33 2 PM32 1 PM31 0 PM30 Address FF23H After reset FFH R/W R/W PM3n I/O mode of P3n pin (n = 0 to 3) Output mode (output buffer is ON) Input mode (output buffer is OFF) 0 1 142 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER 7.4 8-Bit Timer Operation 7.4.1 Operation as 8-bit timer counter Timer 50 and timer 60 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counter. * * * (1) Interval timer with 8-bit resolution External event counter with 8-bit resolution (timer 60 only) Square wave output with 8-bit resolution Operation as interval timer with 8-bit resolution The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (CRn0). To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0). <2> Disable timer output of TOn0 (TOEn0 = 0). <3> Set a count value in CRn0. <4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 7-4 and 7-5). <5> Set the count clock for timer n0 (see Tables 7-3 to 7-6). <6> Enable the operation of TMn0 (TCEn0 = 1). When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated. Tables 7-3 to 7-6 show interval time, and Figures 7-8 to 7-13 show the timing of the interval timer operation. Caution Remark Be sure to stop the timer operation before overwriting the count clock with different data. n = 5, 6 User's Manual U15075EJ1V0UM00 143 CHAPTER 7 8-BIT TIMER Table 7-3. Interval Time of Timer 50 TCL502 TCL501 TCL500 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Minimum Interval Time 1/fX (0.2 s) 2 /fX (1.6 s) 3 8 Maximum Interval Time 2 /fX (51.2 s) 2 /fX (409.6 s) 11 Resolution 1/fX (0.2 s) 2 /fX (1.6 s) 3 2 /fX (25.6 s) 7 2 /fX (6.55 ms) 2 /fXT (7.81 ms) Input cycle of timer 60 match signal x 8 Input cycle of timer 60 output x8 8 15 2 /fX (25.6 s) 7 1/fXT (30.5 s) Input cycle of timer 60 match signal Input cycle of timer 60 output 1/fXT (30.5 s) Input cycle of timer 60 match signal Input cycle of timer 60 1 0 1 Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency Table 7-4. Interval Time of Timer 60 TCL602 TCL601 TCL600 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Minimum Interval Time 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 8 Maximum Interval Time 2 /fX (51.2 s) 2 /fX (1.02 s) 9 Resolution 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle x 2 8 fTMI input cycle 8 fTMI/2 input cycle x 2 2 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 8 8 Remark fX: Main system clock oscillation frequency 144 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) t Count clock TMn0 00H 01H N 00H Clear 01H N 00H Clear N 01H N 00H Clear 01H 00H CRn0 TCEn0 Count start INTTMn0 Interrupt acknowledgement TOnm Interval time Interval time Interval time Interrupt acknowledgement Interrupt acknowledgement Count stop Remarks 1. Interval time = (N + 1) x t: N = 00H to FFH 2. n = 5, 6 nm = 50, 60, 61 Figure 7-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H) Count clock TMn0 00H CRn0 00H TCEn0 Count start INTTMn0 TOnm Remark n = 5, 6 nm = 50, 60, 61 User's Manual U15075EJ1V0UM00 145 CHAPTER 7 8-BIT TIMER Figure 7-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 00H 01H FFH 00H Clear 01H FFH 00H Clear 01H FFH 00H Clear 01H FFH CRn0 FFH TCEn0 Count start INTTMn0 TOnm Remark n = 5, 6 nm = 50, 60, 61 Figure 7-11. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) Count clock TMn0 00H 01H N 00H Clear N M 00H Clear M N M 00H Clear 01H CRn0 N TCEn0 Count start INTTMn0 Interrupt acknowledgement TOnm Interrupt acknowledgement CRn0 overwritten Remark n = 5, 6 nm = 50, 60, 61 146 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-12. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) Count clock TMn0 N-1 N 00H Clear M N FFH 00H Clear M M 00H Clear M 00H CRn0 N TCEn0 H TMn0 overflows because M < N INTTMn0 TOnm CRn0 overwritten Remark n = 5, 6 nm = 50, 60, 61 User's Manual U15075EJ1V0UM00 147 CHAPTER 7 8-BIT TIMER Figure 7-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 60 Match Signal Is Selected for Timer 50 Count Clock) Timer 60 count clock TM60 00H 01H N 00H Clear M 00H Clear M 00H Clear M 00H Clear CR60 N M TCE60 Count start INTTM60 Input clock to timer 50 (timer 60 match signal) Y-1 Y 00H 00H TM50 00H 01H Y CR50 Y TCE50 Count start INTTM50 TO60 TO50 148 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER (2) Operation as external event counter with 8-bit resolution (timer 60 only) The external event counter counts the number of external clock pulses input to the TMI60/P31/INTP1/TO50 pin by using 8-bit timer counter 60 (TM60). To operate timer 60 as an external event counter, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter 60 (TM60) (TCE60 = 0). <2> Disable timer output of TO60 (TOE60 = 0). <3> Set P31 to input mode (PM31 = 1). <4> Select the external input clock for timer 60 (see Table 7-5). <5> Set the operation mode of timer 60 to 8-bit timer counter mode (see Figures 7-4 and 7-5). <6> Set a count value in CR60. <7> Enable the operation of TM60 (TCE60 = 1). Each time the valid edge is input, the value of TM60 is incremented. When the count value of TM60 matches the value set in CR60, TM60 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM60) is generated. Figure 7-14 shows the timing of the external event counter operation. Caution Be sure to stop the timer operation before overwriting the count clock with different data. User's Manual U15075EJ1V0UM00 149 CHAPTER 7 8-BIT TIMER Figure 7-14. Timing of Operation of External Event Counter with 8-Bit Resolution TMI60 pin input TM60 count value 00H 01H 02H 03H 04H 05H N-1 N 00H 01H 02H 03H CR60 N TCE60 INTTM60 Remark N = 00H to FFH 150 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER (3) Operation as square-wave output with 8-bit resolution Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register n0 (CRn0). To operate timer n0 for square-wave output, settings must be made in the following sequence. <1> When using timer 50, set P31 to output mode (PM31 = 0). When using timer 60, set P32 to output mode (PM32 = 0) or set P33 to output mode (PM33 = 0) (When TO61 is selected as timer output). <2> Set the output latches of P31, P32, and P33 to 0. <3> Disable operation of timer counter n0 (TMn0) (TCEn0 = 0). <4> Set a count clock for timer n0 and enable output of TOn0 (TOEn0 = 1) <5> Set a count value in CRn0. <6> Enable the operation of TMn0 (TCEn0 = 1). When the count value of TMn0 matches the value set in CRn0, the TOn0 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TMn0 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated. The square-wave output is cleared to 0 by setting TCEn0 to 0. Tables 7-5 and 7-6 show the square-wave output range, and Figure 7-15 shows the timing of square-wave output. Note In the case of timer 60, either TO60 or TO61 can be selected as the timer output pin. If TO61 is selected, set TOE61 = 1. Caution Remark Be sure to stop the timer operation before overwriting the count clock with different data. n = 5, 6 Note . Table 7-5. Square-Wave Output Range of Timer 50 (During fX = 5.0 MHz Operation) TCL502 0 0 0 0 1 TCL501 0 0 1 1 0 TCL500 0 1 0 1 0 Minimum Pulse Width 1/fX (0.2 s) 2 /fX (1.6 s) 3 8 Maximum Pulse Width 2 /fX (51.2 s) 2 /fX (409.6 s) 11 Resolution 1/fX (0.2 s) 2 /fX (1.6 s) 3 2 /fX (25.6 s) 7 2 /fX (6.55 ms) 2 /fXT (7.81 ms) Input cycle of timer 60 match signal x 8 Input cycle of timer 60 output x8 8 15 2 /fX (25.6 s) 7 1/fXT (30.5 s) Input cycle of timer 60 match signal Input cycle of timer 60 output 1/fXT (30.5 s) Input cycle of timer 60 match signal Input cycle of timer 60 1 0 1 Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency User's Manual U15075EJ1V0UM00 151 CHAPTER 7 8-BIT TIMER Table 7-6. Square-Wave Output Range of Timer 60 (During fX = 5.0 MHz Operation) TCL602 TCL601 0 0 0 0 1 1 0 0 1 1 0 0 TCL600 0 1 0 1 0 1 Minimum Pulse Width 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 Maximum Pulse Width 2 /fX (51.2 s) 2 /fX (1.02 ms) fTMI input cycle x 2 8 Resolution 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle 8 9 fTMI/2 input cycle x 2 2 8 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 8 8 Remark fX: Main system clock oscillation frequency Figure 7-15. Timing of Square-Wave Output with 8-Bit Resolution Count clock TMn0 00H 01H N 00H Clear 01H N 00H Clear N 01H N 00H Clear 01H CRn0 TCEn0 Count start INTTMn0 Interrupt acknowledgement TOnm Note Interrupt acknowledgement Interrupt acknowledgement Note The initial value of TOnm is low level when output is enabled (TOEnm = 1). Remark n = 5, 6 nm = 50, 60, 61 152 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER 7.4.2 Operation as 16-bit timer counter Timer 50 and timer 60 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer counter 50 (TM50) is the higher 8 bits and 8-bit timer counter 60 (TM60) is the lower 8 bits. 8-bit timer 60 controls reset and clear. The following modes can be used for the 16-bit timer counter. * * * (1) Interval timer with 16-bit resolution External event counter with 16-bit resolution Square-wave output with 16-bit resolution Operation as interval timer with 16-bit resolution The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 50 (CR50) and 8-bit compare register 60 (CR60). To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter 50 (TM50) and 8-bit timer counter 60 (TM60) (TCE50 = 0, TCE60 = 0). <2> Disable timer output of TO60 (TOE60 = 0). <3> Set the count clock for timer 60 (see Tables 7-5 and 7-6). <4> Set the operation mode of timer 50 and 8-bit timer 60 to 16-bit timer counter mode (see Figures 7-4 and 7-5). <5> Set a count value in CR50 and CR60. <6> Enable the operation of TM50 and TM60 (TCE60 = 1 Note ). Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE60 (the value of TCE50 is invalid). When the count values of TM50 and TM60 match the values set in CR50 and CR60 respectively, both TM50 and TM60 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal (INTTM60) is generated (INTTM50 is not generated). Table 7-7 shows interval time, and Figure 7-16 shows the timing of the interval timer operation. Cautions 1. Be sure to stop the timer operation before overwriting the count clock with different data. 2. In the 16-bit timer counter mode, TO50 cannot be used. Be sure to set TOE50 = 0 to disable TO50 output. User's Manual U15075EJ1V0UM00 153 CHAPTER 7 8-BIT TIMER Table 7-7. Interval Time with 16-Bit Resolution (During fX = 5.0 MHz Operation) TCL602 0 0 0 0 1 1 TCL601 0 0 1 1 0 0 TCL600 0 1 0 1 0 1 Minimum Interval Time 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 Maximum Interval Time 2 /fX (13.1 ms) 2 /fX (26.2 ms) fTMI input cycle x 2 16 17 16 Resolution 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle fTMI/2 input cycle x 2 2 16 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 16 16 Remark fX: Main system clock oscillation frequency 154 User's Manual U15075EJ1V0UM00 Figure 7-16. Timing of Interval Timer Operation with 16-Bit Resolution t Count clock TM60 count value 00H N 7FH 80H FFH 00H 7FH 80H FFH 00H N 00H 7FH 80H FFH 00H N 00H Not cleared because TM50 does not match CR60 User's Manual U15075EJ1V0UM00 Cleared because TM50 and TM60 match simultaneously N N N N N N N N N N CHAPTER 7 8-BIT TIMER TCE60 Count start TM50 count pulse TM50 00H 01H X-1 X 00H X-1 X 00H CR50 X X X INTTM60 Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement TO60 or TO61 Interval time Remark Interval time = (256X + N + 1) x t: X = 00H to FFH, N = 00H to FFH 155 CHAPTER 7 8-BIT TIMER (2) Operation as external event counter with 16-bit resolution The external event counter counts the number of external clock pulses input to the TMI60/P31/INTP1/TO50 pin by TM50 and TM60. To operate as an external event counter with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of TM50 and TM60 (TCE50 = 0, TCE60 = 0). <2> Disable timer output of TO60 (TOE60 = 0). <3> Set P31 to input mode (PM31 = 1). <4> Select the external input clock for timer 60 (see Tables 7-5 and 7-6). <5> Set the operation mode of timer 50 and 8-bit timer 60 to 16-bit timer counter mode (see Figures 7-4 and 7-5). <6> Set a count value in CR50 and CR60. <7> Enable the operation of TM50 and TM60 (TCE60 = 1 Note ). Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE60 (the value of TCE50 is invalid). Each time the valid edge is input, the values of TM50 and TM60 are incremented. When the count values of TM50 and TM60 simultaneously match the values set in CR50 and CR60 respectively, both TM50 and TM60 are cleared to 00H and counting continues. interrupt request signal (INTTM60) is generated (INTTM50 is not generated). Figure 7-17 shows the timing of the external event counter operation. Caution Be sure to stop the timer operation before overwriting the count clock with different data. At the same time, an 156 User's Manual U15075EJ1V0UM00 Figure 7-17. Timing of External Event Counter Operation with 16-Bit Resolution TMI60 pin input TM60 count value 00H N 7FH 80H FFH 00H 7FH 80H FFH 00H N 00H 7FH 80H FFH 00H N 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously N N N N N N User's Manual U15075EJ1V0UM00 CR60 N N N N CHAPTER 7 8-BIT TIMER TCE60 Count start TM50 count pulse TM50 00H 01H X-1 X 00H X-1 X 00H CR50 X X X INTTM60 Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Remark X = 00H to FFH, N = 00H to FFH 157 CHAPTER 7 8-BIT TIMER (3) Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR50 and CR60. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of TM50 and TM60 (TCE50 = 0, TCE60 = 0). <2> Disable output of TO50 and TO60 (TOE50 = 0, TOE60 = 0). <3> Set a count clock for timer 60. <4> Select either TO60 or TO61 as the timer output pin. If TO60 is selected: Set P32 to the output mode (PM32 = 0), set the P32 output latch to 0, and set TO60 to output enable (TO60 = 1). (Use of TO50 is prohibited.) If TO61 is selected: Set P33 to the output mode (PM33 = 0), set the P33 output latch to 0, and set TO61 to output enable (TOE61 = 1). (Use of TO50 is prohibited.) <5> Set count values in CR50 and CR60. <6> Enable the operation of TM60 (TCE60 = 1 Note ). Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE60 (the value of TCE50 is invalid). When the count values of TM50 and TM60 simultaneously match the values set in CR50 and CR60 respectively, the TO60 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TM50 and TM60 are cleared to 00H and counting continues. At the same time, an interrupt request signal (INTTM60) is generated (INTTM50 is not generated). The square-wave output is cleared to 0 by setting TCE60 to 0. Table 7-8 shows the square wave output range, and Figure 7-18 shows timing of square wave output. Cautions 1. Be sure to stop the timer operation before overwriting the count clock with different data. 2. In the 16-bit timer counter mode, TO50 cannot be used. Be sure to set TOE50 = 0 to disable TO50 output. Remark Items in parentheses are for when the TO61 pin is selected for timer output. Table 7-8. Square-Wave Output Range with 16-Bit Resolution (During fX = 5.0 MHz Operation) TCL602 TCL601 0 0 0 0 1 1 0 0 1 1 0 0 TCL600 0 1 0 1 0 1 Minimum Pulse Width 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 Maximum Pulse Width 2 /fX (13.1 ms) 2 /fX (26.2 ms) fTMI input cycle x 2 16 Resolution 1/fX (0.2 s) 2/fX (0.4 s) fTMI input cycle 16 17 fTMI/2 input cycle x 2 2 16 fTMI/2 input cycle fTMI/2 input cycle fTMI/2 input cycle 3 2 fTMI/2 input cycle x 2 fTMI/2 input cycle x 2 3 16 16 Remark fX: Main system clock oscillation frequency 158 User's Manual U15075EJ1V0UM00 Figure 7-18. Timing of Square-Wave Output with 16-Bit Resolution Count clock TM60 count value 00H N 7FH 80H FFH 00H 7FH 80H FFH 00H N 00H 7FH 80H FFH 00H N 00H Not cleared because TM50 does not match CR60 N N N N N N Cleared because TM50 and TM60 match simultaneously N N N N User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER TCE60 Count start TM50 count pulse TM50 00H 01H X-1 X 00H X-1 X 00H CR50 X X X INTTM60 Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement TO60 or TO61 Note Note The initial value of TO60 or TO61 is low level when output is enabled. 159 Remark X = 00H to FFH, N = 00H to FFH CHAPTER 7 8-BIT TIMER 7.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM60 can be output in the cycle set in TM50. To operate timer 50 and timer 60 as carrier generators, settings must be made in the following sequence. <1> Disable operation of TM50 and TM60 (TCE50 = 0, TCE60 = 0). <2> Disable timer output of TO50 and TO60 (TOE50 = 0, TOE60 = 0). <3> Set count values in CR50, CR60, and CRH60. <4> Set the operation mode of timer 50 and timer 60 to carrier generator mode (see Figures 7-4 and 7-5). <5> Set the count clock for timer 50 and timer 60. <6> Set remote control output to carrier pulse (RMC60 (bit 2 of carrier generator output control register 60 (TCA60)) = 0). Input the required value to NRZB60 (bit 1 of TCA60) by program. Input a value to NRZ60 (bit 0 of TCA60) before it is reloaded from NRZB60. <7> Select either TO60 or TO61 as the timer output pin. If TO60 is selected: Set P32 to the output mode (PM32 = 0), set the P32 output latch to 0, and set TOE60 to output enable (TOE60 = 1). If TO61 is selected: Set P33 to the output mode (PM33 = 0), set the P33 output latch to 0, and set TOE61 to output enable (TOE60 = 1). <8> Enable the operation of TM50 and TM60 (TCE50 = 1, TCE60 = 1). The operation of the carrier generator is as follows. <1> When the count value of TM60 matches the value set in CR60, an interrupt request signal (INTTM60) is generated and output of timer 60 is inverted, which makes the compare register switch from CR60 to CRH60. <2> After that, when the count value of TM60 matches the value set in CRH60, an interrupt request signal (INTTM60) is generated and output of timer 60 is inverted again, which makes the compare register switch from CRH60 to CR60. <3> The carrier clock is generated by repeating <1> and <2> above. <4> When the count value of TM50 matches the value set in CR50, an interrupt request signal (INTTM50) is generated. The rising edge of INTTM50 is the data reload signal of NRZB60 and is transferred to NRZ60. <5> When NRZ60 is 1, a carrier clock is output from the TO60 pin (or the TO61 pin). Cautions 1. TCA60 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit memory manipulation instruction. 2. When setting the carrier generator operation again after stopping it once, reset NRZB60 because the previous value is not retained. In this case also a 1-bit memory manipulation instruction cannot be used. Be sure to use an 8-bit memory manipulation instruction. Figures 7-19 to 7-21 show the operation timing of the carrier generator. 160 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-19. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M > N)) Count clock TM60 count value 00H 01H N 00H Clear N M 00H Clear N 00H Clear N M 00H Clear CR60 N CRH60 M TCE60 Count start INTTM60 Carrier clock Count pulse TM50 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H CR50 TCE50 INTTM50 NRZB60 0 1 0 1 0 NRZ60 0 1 0 1 0 Carrier clock TO60 or TO61 User's Manual U15075EJ1V0UM00 161 CHAPTER 7 8-BIT TIMER Figure 7-20. Timing of Carrier Generator Operation (When CR60 = N, CRH60 = M (M < N), Phases of Carrier Clock and NRZ60 Are Asynchronous) Count clock TM60 count value 00H M N 00H Clear M 00H Clear M N 00H Clear M 00H Clear CR60 N CRH60 M TCE60 Count start INTTM60 Carrier clock Count pulse TM50 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H CR50 TCE50 INTTM50 NRZB60 0 1 0 1 0 NRZ60 0 1 0 1 0 Carrier clock TO60 or TO61 162 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-21. Timing of Carrier Generator Operation (When CR60 = CRH60 = N) Count clock TM60 count value 00H N 00H Clear N 00H Clear N 00H Clear N 00H Clear N 00H Clear N CR60 N CRH60 N TCE60 Count start INTTM60 Carrier clock Count pulse TM50 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H CR50 TCE50 INTTM50 NRZB60 0 1 0 1 0 NRZ60 0 1 0 1 0 Carrier clock TO60 or TO61 User's Manual U15075EJ1V0UM00 163 CHAPTER 7 8-BIT TIMER 7.4.4. PWM free-running mode operation (timer 50) In the PWM free-running mode, TO50 becomes high level when TM50 overflows, and TO50 becomes low level when CR50 and TM50 match. It is thus possible to output a pulse with any duty ratio. To operate timer 50 in the PWM free-running mode, setting must be made in the following sequence. <1> Disable operation of TM50 (TCE50 = 0). <2> Disable timer output of TO50 (TOE50 = 0). <3> Set a count value to CR50. <4> Set the operation mode of timer 50 to the PWM free-running mode. (see Figure 7-4.) <5> Set the count clock for timer 50. <6> Set P31 to the output mode (PM31 = 0) and the P31 output latch to 0 and enable timer output of TO50 (TOE50 = 1). <7> Enable the operation of TM50 (TCE50 = 1). The operation in the PWM free-running mode is as follows. <1> When the count value of TM50 matches the value set in CR50, an interrupt request signal (INTTM50) is generated and a low level is output by the TO50. The TM50 continues counting without being cleared. <2> TO50 outputs a high level when the TM50 overflows. A pulse of any duty is output by repeating the above procedure. Figures 7-22 to 7-25 show the operation timing in the PWM free-running mode. 164 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-22. Operation Timing in PWM Free-Running Mode (When Rising Edge Is Selected) Count clock TM50 00H 01H N FFH 00H Overflow N FFH 00H Overflow N CR50 N TCE50 Count start INTTM50 TO50 Caution When the rising edge is selected, do not set the CR50 to 00H. If the CR50 is set to 00H, PWM output may not be performed normally. Figure 7-23. Operation Timing When Overwriting CR50 (When Rising Edge Is Selected) (1/2) (1) When setting CR50 > TM50 after overflow Count clock TM50 00H 01H N FFH 00H 01H M FFH 00H Overflow Overflow CR50 N Overflow M TCE50 Count start INTTM50 TO50 CR50 overwrite User's Manual U15075EJ1V0UM00 165 CHAPTER 7 8-BIT TIMER Figure 7-23. Operation Timing When Overwriting CR50 (When Rising Edge Is Selected) (2/2) (2) When setting CR50 < TM50 after overflow Count clock TM50 00H 01H N FFH 00H 01H 02H FFH 00H 01H Overflow CR50 N Overflow Overflow 01H TCE50 Count start INTTM50 TO50 CR50 overwrite Overflow occurs but no change takes place because TO50 is high level. Figure 7-24. Operation Timing in PWM Free-Running Mode (When Both Edges Are Selected) (1/2) (1) CR50 = Even number Count clock TM50 00H 01H 02H 2N FEH FFH 00H 01H 02H 2N Overflow FEH FFH Overflow CR50 Overflow 2N TCE50 Count start INTTM50 TO50 166 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-24. Operation Timing in PWM Free-Running Mode (When Both Edges Are Selected) (2/2) (2) When CR50 = Odd number Count clock TM50 00H 01H 2N + 1 FFH 00H 01H 2N + 1 FFH 00H 01H Overflow CR50 Overflow 2N + 1 Overflow TCE50 Count start INTTM50 TO50 Caution When both edges are selected, do not set CR50 to 00H, 01H, and FFH. If the CR50 is set to these values, PWM output may not be performed normally. Figure 7-25. Operation Timing in PWM Free-Running Mode (When Both Edges Are Selected) (When CR50 Is Overwritten) Count clock TM50 00H 01H 02H 2N FEH FFH 00H 01H 2N + 1 FFH 00H 01H Overflow CR50 2N Overflow 2N + 1 Overflow TCE50 Count start INTTM50 TO50 CR50 overwrite User's Manual U15075EJ1V0UM00 167 CHAPTER 7 8-BIT TIMER 7.4.5 Operation as PWM output (timer 60) In the PWM pulse generator mode, a pulse of any duty ratio can be output by setting a low-level width using CR60 and a high-level width using CRH60. To operate timer 60 in PWM output mode, settings must be made in the following sequence. <1> Disable operation of TM60 (TCE60 = 0). <2> Disable timer output of TO60 (TOE60 = 0). <3> Set count values in CR60 and CRH60. <4> Set the operation mode of timer 60 to the PWM pulse generator mode (see Figure 7-5). <5> Set the count clock for timer 60. <6> Set P32 to the output mode (PM32 = 0) and the P32 output latch to 0 and enable timer output of TO60 (TOE60 = 1). <7> Enable the operation of TM60 (TCE60 = 1). The operation in the PWM output mode is as follows. <1> When the count value of TM60 matches the value set in CR60, an interrupt request signal (INTTM60) is generated and output of timer 60 is inverted, which makes the compare register switch from CR60 to CRH60. <2> A match between TM60 and CR60 clears the TM60 value to 00H and then counting starts again. <3> After that, when the count value of TM60 matches the value set in CRH60, an interrupt request signal (INTTM60) is generated and output of timer 60 is inverted again, which makes the compare register switch from CRH60 to CR60. <4> A match between TM60 and CRH60 clears the TM60 value to 00H and then counting starts again. A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 7-26 and 7-27 show the operation timing in the PWM output mode. 168 User's Manual U15075EJ1V0UM00 CHAPTER 7 8-BIT TIMER Figure 7-26. PWM Pulse Generator Mode Timing (Basic Operation) Count clock TM60 count value 00H 01H N 00H Clear 01H M 00H Clear 01H N 00H Clear 01H M 00H Clear CR60 N CRH60 M TCE60 Count start INTTM60 TO60 or TO61Note Note The initial value of TO60 is low level when output is enabled (TOE60 = 1). Figure 7-27. PWM Output Mode Timing (When CR60 and CRH60 Are Overwritten) Count clock TM60 count value 00H 01H N 00H Clear Y 00H Clear X N X 00H Clear M 00H Clear X CR60 N CRH60 M Y M TCE60 Count start INTTM60 TO60 or TO61Note Note The initial value of TO60 is low level when output is enabled (TOE60 = 1). User's Manual U15075EJ1V0UM00 169 CHAPTER 7 8-BIT TIMER 7.5 Notes on Using 8-Bit Timer (1) Error on starting timer An error of up to 1 clock is included in the time between the timer being started and a match signal being generated. This is because 8-bit timer counter n0 (TMn0) is started asynchronously to the count pulse. Figure 7-28. Start Timing of 8-Bit Timer Counter Count pulse TMn0 count value 00H 01H 02H 03H 04H Timer start Remark (2) n = 5, 6 Setting of 8-bit compare register n0 8-bit compare register n0 (CRn0) can be set to 00H. Therefore, one pulse can be counted when the 8-bit timer operates as an event counter. Figure 7-29. Timing of Operation as External Event Counter (8-Bit Resolution) TMI60 input CR60 00H TM60 count value Interrupt request flag 00H 00H 00H 00H 170 User's Manual U15075EJ1V0UM00 CHAPTER 8 WATCH TIMER 8.1 Watch Timer Functions The watch timer has the following functions. * Watch timer * Interval timer The watch and interval timers can be used at the same time. Figure 8-1 is a block diagram of the watch timer. Figure 8-1. Block Diagram of Watch Timer Clear Selector fX/2 7 fW fW 24 9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29 5-bit counter Clear INTWT fXT Selector INTWTI WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus User's Manual U15075EJ1V0UM00 171 CHAPTER 8 WATCH TIMER (1) Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used instead. (2) Interval timer The interval timer is used to generate an interrupt request (INTWTI) at specified intervals. Table 8-1. Interval Generated Using the Interval Timer Interval 2 x 1/fW 4 At fX = 5.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms At fX = 4.19 MHz 489 s 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms At fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 2 x 1/fW 5 2 x 1/fW 6 7 2 x 1/fW 2 x 1/fW 8 2 x 1/fW 9 7 Remarks 1. fW: Watch timer clock frequency (fX/2 or fXT) 2. fX: Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 8.2 Watch Timer Configuration The watch timer includes the following hardware. Table 8-2. Watch Timer Configuration Item Counter Prescaler Control register 5 bits x 1 9 bits x 1 Watch timer mode control register (WTM) Configuration 172 User's Manual U15075EJ1V0UM00 CHAPTER 8 WATCH TIMER 8.3 Watch Timer Control Register The watch timer is controlled by the watch timer mode control register (WTM). * Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled. WTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WTM to 00H. Figure 8-2. Format of Watch Timer Mode Control Register Symbol WTM 7 WTM7 6 WTM6 5 WTM5 4 WTM4 3 0 2 0 1 WTM1 0 WTM0 Address FF4AH After reset 00H R/W R/W WTM7 0 1 fX/2 (39.1 kHz) fXT (32.768 kHz) 7 Watch timer count clock selection WTM6 0 0 0 0 1 1 WTM5 0 0 1 1 0 0 WTM4 0 1 0 1 0 1 2 /fW (488 s) 4 Prescaler interval selection 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) Setting prohibited Other than above WTM1 0 1 Cleared after stop Started Control of 5-bit counter operation WTM0 0 1 Watch timer operation Operation disabled (both prescaler and timer cleared) Operation enabled 7 Remarks 1. fW: Watch timer clock frequency (fX/2 or fXT) 2. fX: Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 4. The parenthesized values apply to operation at fW = 32.768 kHz. User's Manual U15075EJ1V0UM00 173 CHAPTER 8 WATCH TIMER 8.4 Watch Timer Operation 8.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. The watch timer is used to generate an interrupt request at specified intervals. By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting. It is possible to start the watch timer only from zero seconds by clearing WTM1 to 0 when the interval timer and watch timer operate at the same time. In this case, however, an error of up to 29 x 1/fW seconds may occur in the overflow (INTWT) after the zero-second start of the watch timer because the 9-bit prescaler is not cleared to 0. 8.4.2 Operation as interval timer The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value. The interval can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM). Table 8-3. Interval Time of Interval Timer WTM6 0 0 0 0 1 1 WTM5 0 0 1 1 0 0 Other than above WTM4 0 1 0 1 0 1 4 Interval 2 x 1/fW 2 x 1/fW 5 At fX = 5.0 MHz 409.6 s 819.2 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms At fX = 4.19 MHz 489 s 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms At fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 2 x 1/fW 6 7 2 x 1/fW 2 x 1/fW 8 2 x 1/fW 9 Setting prohibited Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. fW: Watch timer clock frequency 174 User's Manual U15075EJ1V0UM00 CHAPTER 8 WATCH TIMER Figure 8-3. Watch Timer/Interval Timer Operation Timing 5-bit counter 0H Start Count clock fW/29 Watch timer interrupt INTWT Interval timer interrupt INTWTI Interval timer (T) T Overflow Overflow Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s) Caution When operation of the watch timer and 5-bit counter operation is enabled by setting bit 0 (WTM0) of the watch mode timer mode control register (WTM) to 1, the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with WTM3 (bit 3 of WTM). This is because there is a delay of one 9-bit prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the INTWT signal is generated at the specified intervals. Remarks 1. fW: Watch timer clock frequency 2. The parenthesized values apply to operation at fW = 32.768 kHz. User's Manual U15075EJ1V0UM00 175 [MEMO] 176 User's Manual U15075EJ1V0UM00 CHAPTER 9 WATCHDOG TIMER 9.1 Watchdog Timer Functions The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect a program runaway. When a runaway is detected, a non-maskable interrupt or the RESET signal can be generated. Table 9-1. Watchdog Timer Runaway Detection Time Runaway Detection Time 11 2 x 1/fX At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 2 x 1/fX 17 fX: Main system clock oscillation frequency (2) Interval timer The interval timer generates an interrupt at an arbitrary preset interval. Table 9-2. Interval Time Interval 11 2 x 1/fX At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 2 x 1/fX 17 fX: Main system clock oscillation frequency User's Manual U15075EJ1V0UM00 177 CHAPTER 9 WATCHDOG TIMER 9.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 9-3. Configuration of Watchdog Timer Item Control registers Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Configuration Figure 9-1. Block Diagram of Watchdog Timer Internal bus fX 24 fX 26 Prescaler fX 28 fX 210 TMMK4 TMIF4 INTWDT Maskable interrupt request RESET INTWDT Non-maskable interrupt request Selector 7-bit counter Clear Controller 3 TCL22 TCL21 TCL20 Watchdog timer clock select register (WDCS) RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus 178 User's Manual U15075EJ1V0UM00 CHAPTER 9 WATCHDOG TIMER 9.3 Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers. * Watchdog timer clock select register (WDCS) * Watchdog timer mode register (WDTM) (1) Watchdog timer clock select register (WDCS) This register sets the watchdog timer count clock. WDCS is set with an 8-bit memory manipulation instruction. RESET input sets WDCS to 00H. Figure 9-2. Format of Watchdog Timer Clock Select Register Symbol WDCS 7 0 6 0 5 0 4 0 3 0 2 WDCS2 1 WDCS1 0 WDCS0 Address FF42H After reset 00H R/W R/W WDCS2 0 0 1 1 WDCS1 0 1 0 1 WDCS0 0 0 0 0 Watchdog timer count clock selection fX/24 (312.5 kHz) 211/fX (410 s) Interval fX/26 (78.1 kHz) fX/28 (19.5 kHz) fX/210 (4.88 kHz) Setting prohibited 213/fX (1.64 ms) 215/fX (6.55 ms) 217/fX (26.2 ms) Other than above Remarks 1. fX : Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U15075EJ1V0UM00 179 CHAPTER 9 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer Mode Register Symbol WDTM <7> RUN 6 0 5 0 4 WDTM4 3 WDTM3 2 0 1 0 0 0 Address FFF9H After reset 00H R/W R/W RUN 0 1 Stops counting. Watchdog timer operation selectionNote 1 Clears counter and starts counting. WDTM4 0 0 1 1 WDTM3 0 1 0 1 Operation stop Watchdog timer operation mode selectionNote 2 Interval timer mode (Generates a maskable interrupt upon overflow occurrence.)Note 3 Watchdog timer mode 1 (Generates a non-maskable interrupt upon overflow occurrence.) Watchdog timer mode 2 (Starts reset operation upon overflow occurrence.) Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software. 3. The watchdog timer starts operation as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock select register (WDCS). 2. To set watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming TMIF4 (bit 0 of the interrupt request flag register 0 (IF0)) is set to 0. When watchdog timer mode 1 or 2 is selected with TMIF4 set to 1, a non-maskable interrupt is generated upon the completion of rewriting WDTM4. 180 User's Manual U15075EJ1V0UM00 CHAPTER 9 WATCHDOG TIMER 9.4 Watchdog Timer Operation 9.4.1 Operation as watchdog timer The watchdog timer detects a program runaway when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of watchdog timer clock select register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the runaway detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the watchdog timer before executing the STOP instruction. Cautions 1. The actual runaway detection time may be up to 0.8% shorter than the set time. 2. When the subsystem clock is selected as the CPU clock, the watchdog timer count operation is stopped. Even when the main system clock continues oscillating in this case, watchdog timer count operation is stopped. Table 9-4. Watchdog Timer Runaway Detection Time WDCS2 WDCS1 WDCS0 0 0 1 1 0 1 0 1 0 0 0 0 Runaway Detection Time 11 2 x 1/fX At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 2 x 1/fX 17 fX: Main system clock oscillation frequency User's Manual U15075EJ1V0UM00 181 CHAPTER 9 WATCHDOG TIMER 9.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value. Select a count clock (or interval) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to clear the interval timer before executing the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless the RESET signal is input. 2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been set. Table 9-5. Interval Time of Interval Timer WDCS2 WDCS1 WDCS0 0 0 1 1 0 1 0 1 0 0 0 0 11 2 x 1/fX Interval At fX = 5.0 MHz 410 s 1.64 ms 6.55 ms 26.2 ms 2 x 1/fX 13 2 x 1/fX 15 2 x 1/fX 17 fX: Main system clock oscillation frequency 182 User's Manual U15075EJ1V0UM00 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) 10.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter used to convert analog inputs into digital signals. This converter can control six channels (ANI0 to ANI5) of analog inputs. A/D conversion can only be started by software. One of analog inputs ANI0 to ANI5 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time A/D conversion is complete. 10.2 8-Bit A/D Converter Configuration The 8-bit A/D converter includes the following hardware. Table 10-1. Configuration of 8-Bit A/D Converter Item Analog inputs Registers 6 channels (ANI0 to ANI5) Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) A/D converter mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) Configuration Control registers User's Manual U15075EJ1V0UM00 183 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) Figure 10-1. Block Diagram of 8-Bit A/D Converter AVDD ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 P-ch Sample & hold circuit Voltage comparator Tap selector Selector AVSS AVSS Successive approximation register (SAR) Controller INTAD0 3 ADS02 ADS01 ADS00 ADCS0 FR02 FR01 FR00 A/D conversion result register 0 (ADCR0) Analog input channel specification register 0 (ADS0) Internal bus A/D converter mode register 0 (ADM0) (1) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0). (2) A/D conversion result register 0 (ADCR0) ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result in the successive approximation register is loaded into ADCR0, which is an 8-bit register. ADCR0 can be read with an 8-bit memory manipulation instruction. RESET input makes ADCR0 undefined. (3) Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. 184 User's Manual U15075EJ1V0UM00 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. (5) Series resistor string The series resistor string is configured between AVDD and AVSS. It generates the reference voltages with which analog inputs are compared. (6) ANI0 to ANI5 Pins ANI0 to ANI5 are the 6-channel analog input pins for the A/D converter. They are used to receive the analog signals for A/D conversion. Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range. If a voltage greater than AVDD or less than AVSS (even if within the absolute maximum rating) is applied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected. (7) AVSS pin The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS pin, even while the A/D converter is not being used. (8) AVDD pin The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD pin, even while the A/D converter is not being used. User's Manual U15075EJ1V0UM00 185 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) 10.3 8-Bit A/D Converter Control Registers The 8-bit A/D converter is controlled by the following two registers. * A/D converter mode register 0 (ADM0) * Analog input channel specification register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM0 to 00H. Figure 10-2. Format of A/D Converter Mode Register 0 Symbol ADM0 <7> ADCS0 6 0 5 FR02 4 FR01 3 FR00 2 0 1 0 0 0 Address FF80H After reset 00H R/W R/W ADCS0 0 1 Conversion disabled Conversion enabled A/D conversion control FR02 0 0 0 1 1 1 FR01 0 0 1 0 0 1 FR00 0 1 0 0 1 0 144/fX 120/fX 96/fX 72/fX 60/fX 48/fX (28.8 s) (24 s) (19.2 s) (14.4 s) A/D conversion time selectionNote 1 (Setting prohibitedNote 2) (Setting prohibitedNote 2) Other than above Setting prohibited Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14 s. 2. These bit combinations must not be used, as the A/D conversion time will fall below 14 s. Cautions 1. Bits 0 to 2 and 6 must be set to 0. 2. The result of conversion performed immediately after setting ADCS0 is undefined. 3. The conversion result may be undefined after clearing ADCS0. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 186 User's Manual U15075EJ1V0UM00 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) (2) Analog input channel specification register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADS0 to 00H. Figure 10-3. Format of Analog Input Channel Specification Register 0 Symbol ADS0 7 0 6 0 5 0 4 0 3 0 2 ADS02 1 ADS01 0 ADS00 Address FF84H After reset 00H R/W R/W ADS02 0 0 0 0 1 1 ADS01 0 0 1 1 0 0 ADS00 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 Setting prohibited Analog input channel specification Other than above Caution Bits 3 to 7 must be set to 0. User's Manual U15075EJ1V0UM00 187 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) 10.4 8-Bit A/D Converter Operation 10.4.1 Basic operation of 8-bit A/D converter <1> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 7 of the successive approximation register (SAR) is set. The series resistor string tap voltage at the tap selector is set to half of AVDD. <5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half of AVDD, the MSB of SAR is left set. If it is lower than half of AVDD, the MSB is reset. <6> Bit 6 of SAR is set automatically, and comparison shifts to the next stage. The next tap voltage of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows: * Bit 7 = 1: Three quarters of AVDD * Bit 7 = 0: One quarter of AVDD The tap voltage is compared with the analog input voltage. Bit 6 is set or reset according to the result of comparison. * Analog input voltage tap voltage: Bit 6 = 1 * Analog input voltage < tap voltage: Bit 6 = 0 <7> Comparison is repeated until bit 0 of SAR is reached. <8> When comparison is completed for all of the 8 bits, a significant digital result is left in SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The first A/D conversion value immediately after A/D conversion has been started may be undefined. 2. In standby mode, A/D converter operation is stopped. 188 User's Manual U15075EJ1V0UM00 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) Figure 10-4. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined 80H C0H or 40H Conversion result ADCR0 Conversion result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if ADCS0 is set (1). RESET input makes A/D conversion result register 0 (ADCR0) undefined. 10.4.2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins (ANI0 to ANI5) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) are represented by: ADCR0 = INT ( or (ADCR0 - 0.5) x INT( ): VIN: AVDD: ADCR0: AVDD AVDD VIN < (ADCR0 + 0.5) x 256 256 VIN x 256 + 0.5) AVDD Function that returns the integer part of a parenthesized value Analog input voltage Supply voltage for the A/D converter Value in A/D conversion result register 0 (ADCR0) Figure 10-5 shows the relationship between the analog input voltage and the A/D conversion result. User's Manual U15075EJ1V0UM00 189 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) Figure 10-5. Relationship Between Analog Input Voltage and A/D Conversion Result 255 254 253 A/D conversion result (ADCR0) 3 2 1 0 1 3 2 5 3 1 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1 Input voltage/AVDD 190 User's Manual U15075EJ1V0UM00 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) 10.4.3 Operation mode of 8-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI5 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 1 triggers A/D conversion for a voltage applied to the analog input pin specified in analog input channel specification register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the ongoing session of A/D conversion is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written to ADM0 again during A/D conversion, A/D conversion is stopped immediately. Figure 10-6. Software-Started A/D Conversion Rewriting ADM0 ADCS0 = 1 Rewriting ADM0 ADCS0 = 1 ADCS0 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion is discontinued; no conversion result is preserved. Stop ADCR0 ANIn ANIn ANIm INTAD0 Remarks 1. n = 0 to 5 2. m = 0 to 5 User's Manual U15075EJ1V0UM00 191 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) 10.5 Cautions Related to 8-Bit A/D Converter (1) Current consumption in standby mode In standby mode, the A/D converter stops operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 10-7 shows how to reduce the current consumption in standby mode. Figure 10-7. How to Reduce Current Consumption in Standby Mode AVDD P-ch ADCS0 Series resistor string AVSS (2) Input range for pins ANI0 to ANI5 Be sure to keep the input voltage at ANI0 to ANI5 within the rating. If a voltage not lower than AVDD or not higher than AVSS (even within the absolute maximum rating) is input into a conversion channel, the conversion output of the channel becomes undefined, which may affect the conversion output of the other channels. (3) Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from ADCR0 using instruction Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0. <2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0 (ADM0) or analog input channel specification register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. ADCR0 is not written to. No A/D conversion end interrupt request signal (INTAD0) is generated. (4) Conversion result immediately after start of A/D conversion The first A/D conversion value immediately after A/D conversion has been started is undefined. Poll the A/D conversion end interrupt request (INTAD0) and drop the first conversion result. 192 User's Manual U15075EJ1V0UM00 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) (5) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress. To read the A/D conversion result after the A/D conversion operation has been stopped, stop the A/D conversion operation before the next conversion operation is completed. Figures 10-8 and 10-9 show the timing at which the conversion result is read. Figure 10-8. Conversion Result Read Timing (If Conversion Result Is Undefined) End of A/D conversion End of A/D conversion ADCR0 INTAD0 ADCS0 Normal conversion result Undefined value Normal conversion result is read. A/D conversion stops. Undefined value is read. Figure 10-9. Conversion Result Read Timing (If Conversion Result Is Normal) End of A/D conversion ADCR0 INTAD0 ADCS0 Normal conversion result A/D conversion stops. Normal conversion result is read. User's Manual U15075EJ1V0UM00 193 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) (6) Noise prevention To maintain a resolution of 8 bits, watch for noise to the AVDD and ANI0 to ANI5 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 10-10. Figure 10-10. Analog Input Pin Treatment If noise not lower than AVDD or not higher than AVSS is likely to come to the AVDD pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower). VDD AVDD C = 100 to 1,000 pF AVSS VSS (7) ANI0 to ANI5 The analog input pins (ANI0 to ANI5) are alternate-function pins. They are also used as port pins (P60 to P65). If any of ANI0 to ANI5 has been selected for A/D conversion, do not execute input instructions for the ports; otherwise the conversion resolution may be reduced. If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise may occur that prevents an A/D conversion result from being obtained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pins during A/D conversion. (8) Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the A/D conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In this case, ADIF0 may already be set if it is read-accessed immediately after ADM0 is write-accessed, even when A/D conversion has not been completed for the new analog input. In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand. 194 User's Manual U15075EJ1V0UM00 CHAPTER 10 8-BIT A/D CONVERTER (PD789426 AND 789446 SUBSERIES) Figure 10-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 (to begin conversion for ANIn) Rewriting to ADM0 (to begin conversion for ANIm) ADIF0 has been set, but conversion for ANIm has not been completed. A/D conversion ANIn ANIn ANIm ANIm ADCR0 ANIn ANIn ANIm ANIm INTAD0 Remarks 1. n = 0 to 5 2. m = 0 to 5 (9) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI5 input circuit. If your application is designed to be changed to backup power, the AVDD pin must be supplied with the same voltage level as the VDD pin, as shown in Figure 10-12. Figure 10-12. AVDD Pin Handling VDD AVDD Main power source Backup capacitor VSS AVSS (10) AVDD pin input impedance A series resistor string of several ten of k is connected between the AVDD and AVSS pins. Consequently, if the output impedance of the reference voltage supply is high, the reference voltage supply will form a parallel connection with the series resistor string, creating a large reference voltage differential. User's Manual U15075EJ1V0UM00 195 [MEMO] 196 User's Manual U15075EJ1V0UM00 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) 11.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter used to convert analog inputs into digital signals. This converter can control six channels (ANI0 to ANI5) of analog inputs. A/D conversion can only be started by software. One of analog inputs ANI0 to ANI5 is selected for A/D conversion. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time A/D conversion is complete. 11.2 10-Bit A/D Converter Configuration The 10-bit A/D converter includes the following hardware. Table 11-1. Configuration of 10-Bit A/D Converter Item Analog inputs Registers 6 channels (ANI0 to ANI5) Successive approximation register (SAR) A/D conversion result register 0 (ADCR0) A/D converter mode register 0 (ADM0) Analog input channel specification register 0 (ADS0) Configuration Control registers User's Manual U15075EJ1V0UM00 197 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) Figure 11-1. Block Diagram of 10-Bit A/D Converter AVDD ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 P-ch Sample & hold circuit Voltage comparator Tap selector Selector AVSS AVSS Successive approximation register (SAR) Controller INTAD0 3 ADS02 ADS01 ADS00 ADCS0 FR02 FR01 FR00 A/D conversion result register 0 (ADCR0) Analog input channel specification register 0 (ADS0) Internal bus A/D converter mode register 0 (ADM0) (1) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (MSB). Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D conversion, the SAR sends its contents to A/D conversion result register 0 (ADCR0). (2) A/D conversion result register 0 (ADCR0) ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result in the successive approximation register is loaded into ADCR0, which is a 10-bit register. ADCR0 can be read with a 16-bit memory manipulation instruction. RESET input makes ADCR0 undefined. ADCR0H (FF14H) ADCR0L (FF14H) 0 0 0 0 0 0 Address After reset R/W FF14H, FF15H 0000H R Symbol Caution When the PD78F9436, a flash memory version of the PD789425 or PD789426, is used, this register can be accessed in 8-bit units. However, only an object file assembled with the PD789425 or PD789426 can be used. The same is also true for the PD78F9456, a flash memory version of the PD789445 or PD789446: This register can be accessed in 8-bit units, but only an object file assembled with the PD789445 or PD789446 can be used. 198 User's Manual U15075EJ1V0UM00 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) (3) Sample & hold circuit The sample & hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. (5) Series resistor string The series resistor string is configured between AVDD and AVSS. against which analog inputs are compared. It generates the reference voltages (6) ANI0 to ANI5 Pins ANI0 to ANI5 are the 6-channel analog input pins for the A/D converter. They are used to receive the analog signals for A/D conversion. Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range. If a voltage greater than AVDD or less than AVSS (even if within the absolute maximum rating) is applied to any of these pins, the conversion value for the corresponding channel will be undefined. Furthermore, the conversion values for the other channels may also be affected. (7) AVSS pin The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as the VSS pin, even while the A/D converter is not being used. (8) AVDD pin The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same potential as the VDD pin, even while the A/D converter is not being used. User's Manual U15075EJ1V0UM00 199 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) 11.3 10-Bit A/D Converter Control Registers The 10-bit A/D converter is controlled by the following two registers. * A/D converter mode register 0 (ADM0) * Analog input channel specification register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion. ADM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM0 to 00H. Figure 11-2. Format of A/D Converter Mode Register 0 Symbol ADM0 <7> ADCS0 6 0 5 FR02 4 FR01 3 FR00 2 0 1 0 0 0 Address FF80H After reset 00H R/W R/W ADCS0 0 1 Conversion disabled Conversion enabled A/D conversion control FR02 0 0 0 1 1 1 FR01 0 0 1 0 0 1 FR00 0 1 0 0 1 0 144/fX 120/fX 96/fX 72/fX 60/fX 48/fX (28.8 s) (24 s) (19.2 s) (14.4 s) A/D conversion time selectionNote 1 (Setting prohibitedNote 2) (Setting prohibitedNote 2) Other than above Setting prohibited Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14 s. 2. These bit combinations must not be used, as the A/D conversion time will fall below 14 s. Cautions 1. Bits 0 to 2 and 6 must be set to 0. 2. The result of conversion performed immediately after setting ADCS0 is undefined. 3. The conversion result may be undefined after clearing ADCS0. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 200 User's Manual U15075EJ1V0UM00 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) (2) Analog input channel specification register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H. Figure 11-3. Format of Analog Input Channel Specification Register 0 Symbol ADS0 7 0 6 0 5 0 4 0 3 0 2 ADS02 1 ADS01 0 ADS00 Address FF84H After reset 00H R/W R/W ADS02 0 0 0 0 1 1 ADS01 0 0 1 1 0 0 ADS00 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 Setting prohibited Analog input channel specification Other than above Caution Bits 3 to 7 must be set to 0. User's Manual U15075EJ1V0UM00 201 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) 11.4 10-Bit A/D Converter Operation 11.4.1 Basic operation of 10-bit A/D converter <1> Select a channel for A/D conversion, using analog input channel specification register 0 (ADS0). <2> The voltage supplied to the selected analog input channel is sampled using the sample & hold circuit. <3> After sampling continues for a certain period of time, the sample & hold circuit is put on hold to keep the input analog voltage until A/D conversion is completed. <4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string tap voltage at the tap selector is set to half of AVDD. <5> The series resistor string tap voltage is compared with the analog input voltage using the voltage comparator. If the analog input voltage is higher than half of AVDD, the MSB of SAR is left set. If it is lower than half of AVDD, the MSB is reset. <6> Bit 8 of SAR is set automatically, and comparison shifts to the next stage. The next tap voltage of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows: * Bit 9 = 1: Three quarters of AVDD * Bit 9 = 0: One quarter of AVDD The tap voltage is compared with the analog input voltage. Bit 8 is set or reset according to the result of comparison. * Analog input voltage tap voltage: Bit 8 = 1 * Analog input voltage < tap voltage: Bit 8 = 0 <7> Comparison is repeated until bit 0 of SAR is reached. <8> When comparison is completed for all of the 10 bits, a significant digital result is left in SAR. This value is sent to and latched in A/D conversion result register 0 (ADCR0). At the same time, it is possible to generate an A/D conversion end interrupt request (INTAD0). Cautions 1. The first A/D conversion value immediately after A/D conversion has been started may be undefined. 2. In standby mode, A/D converter operation is stopped. 202 User's Manual U15075EJ1V0UM00 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) Figure 11-4. Basic Operation of 10-Bit A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined Conversion result ADCR0 Conversion result INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or analog input channel specification register 0 (ADS0) during A/D conversion, the ongoing A/D conversion is canceled. In this case, A/D conversion is restarted from the beginning, if ADCS0 is set (1). RESET input makes A/D conversion result register 0 (ADCR0) undefined. 11.4.2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins (ANI0 to ANI5) and the A/D conversion result (A/D conversion result register 0 (ADCR0)) are represented by: ADCR0 = INT ( or (ADCR0 - 0.5) x INT( ): VIN: AVDD: ADCR0: AVDD AVDD VIN < (ADCR0 + 0.5) x 1,024 1,024 VIN x 1,024 + 0.5) AVDD Function that returns the integer part of a parenthesized value Analog input voltage Supply voltage for the A/D converter Value in A/D conversion result register 0 (ADCR0) Figure 11-5 shows the relationship between the analog input voltage and the A/D conversion result. User's Manual U15075EJ1V0UM00 203 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) Figure 11-5. Relationship Between Analog Input Voltage and A/D Conversion Result 1023 1022 1021 A/D conversion result (ADCR0) 3 2 1 0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 2048 1024 2048 1024 2048 1 Input voltage/AVDD 204 User's Manual U15075EJ1V0UM00 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) 11.4.3 Operation mode of 10-bit A/D converter The A/D converter is initially in select mode. In this mode, analog input channel specification register 0 (ADS0) is used to select an analog input channel from ANI0 to ANI5 for A/D conversion. A/D conversion can be started only by software, that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. * Software-started A/D conversion Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) to 1 triggers A/D conversion for a voltage applied to the analog input pin specified in A/D input selection register 0 (ADS0). Upon completion of A/D conversion, the conversion result is saved to A/D conversion result register 0 (ADCR0). At the same time, an interrupt request signal (INTAD0) is generated. Once A/D conversion is activated, and completed, another session of A/D conversion is started. A/D conversion is repeated until new data is written to ADM0. If data where ADCS0 is 1 is written to ADM0 again during A/D conversion, the ongoing session of A/D conversion is discontinued, and a new session of A/D conversion begins for the new data. If data where ADCS0 is 0 is written to ADM0 again during A/D conversion, A/D conversion is stopped immediately. Figure 11-6. Software-Started A/D Conversion Rewriting ADM0 ADCS0 = 1 Overwriting ADM0 ADCS0 = 1 ADCS0 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion is discontinued; no conversion result is preserved. Stop ADCR0 ANIn ANIn ANIm INTAD0 Remarks 1. n = 0 to 5 2. m = 0 to 5 User's Manual U15075EJ1V0UM00 205 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) 11.5 Cautions Related to 10-Bit A/D Converter (1) Current consumption in standby mode In standby mode, the A/D converter stops operation. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 11-7 shows how to reduce the current consumption in standby mode. Figure 11-7. How to Reduce Current Consumption in Standby Mode AVDD P-ch ADCS0 Series resistor string AVSS (2) Input range for pins ANI0 to ANI5 Be sure to keep the input voltage at ANI0 to ANI5 within the rating. If a voltage not lower than AVDD or not higher than AVSS (even within the absolute maximum rating) is input into a conversion channel, the conversion output of the channel becomes undefined, which may affect the conversion output of the other channels. (3) Conflict <1> Conflict between writing to A/D conversion result register 0 (ADCR0) at the end of conversion and reading from ADCR0 using instruction Reading from ADCR0 takes precedence. After reading, the new conversion result is written to ADCR0. <2> Conflict between writing to ADCR0 at the end of conversion and writing to A/D converter mode register 0 (ADM0) or analog input channel specification register 0 (ADS0) Writing to ADM0 or ADS0 takes precedence. ADCR0 is not written to. No A/D conversion end interrupt request signal (INTAD0) is generated. (4) Conversion result immediately after start of A/D conversion The first A/D conversion value immediately after A/D conversion has been started is undefined. Poll the A/D conversion end interrupt request (INTAD0) and drop the first conversion result. 206 User's Manual U15075EJ1V0UM00 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) (5) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read the A/D conversion result while the A/D conversion operation is in progress. To read the A/D conversion result after the A/D conversion operation has been stopped, stop the A/D conversion operation before the next conversion operation is completed. Figures 11-8 and 11-9 show the timing at which the conversion result is read. Figure 11-8. Conversion Result Read Timing (If Conversion Result Is Undefined) End of A/D conversion End of A/D conversion ADCR0 INTAD0 ADCS0 Normal conversion result Undefined value Normal conversion result is read. A/D conversion stops. Undefined value is read. Figure 11-9. Conversion Result Read Timing (If Conversion Result Is Normal) End of A/D conversion ADCR0 INTAD0 ADCS0 Normal conversion result A/D conversion stops. Normal conversion result is read. User's Manual U15075EJ1V0UM00 207 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) (6) Noise prevention To maintain a resolution of 10 bits, watch for noise to the AVDD and ANI0 to ANI5 pins. The higher the output impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 11-10. Figure 11-10. Analog Input Pin Treatment If noise not lower than AVDD or not higher than AVSS is likely to come to the AVDD pin, clamp the voltage at the pin by attaching a diode with a small VF (0.3 V or lower). VDD AVDD C = 100 to 1,000 pF AVSS VSS (7) ANI0 to ANI5 The analog input pins (ANI0 to ANI5) are alternate-function pins. They are also used as port pins (P60 to P65). If any of ANI0 to ANI5 has been selected for A/D conversion, do not execute input instructions for the ports; otherwise the conversion resolution may be reduced. If a digital pulse is applied to a pin adjacent to the analog input pins during A/D conversion, coupling noise may occur that prevents an A/D conversion result from being obtained as expected. Avoid applying a digital pulse to pins adjacent to the analog input pins during A/D conversion. (8) Interrupt request flag (ADIF0) Changing the contents of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, the A/D conversion result and the conversion end interrupt request flag may reflect the previous analog input immediately before writing to ADM0 occurs. In this case, ADIF0 may already be set if it is read-accessed immediately after ADM0 is write-accessed, even when A/D conversion has not been completed for the new analog input. In addition, when A/D conversion is restarted, ADIF0 must be cleared beforehand. 208 User's Manual U15075EJ1V0UM00 CHAPTER 11 10-BIT A/D CONVERTER (PD789436 AND 789456 SUBSERIES) Figure 11-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 (to begin conversion for ANIn) Rewriting to ADM0 (to begin conversion for ANIm) ADIF0 has been set, but conversion for ANIm has not been completed. A/D conversion ANIn ANIn ANIm ANIm ADCR0 ANIn ANIn ANIm ANIm INTAD0 Remarks 1. n = 0 to 5 2. m = 0 to 5 (9) AVDD pin The AVDD pin is used to supply power to the analog circuit. It is also used to supply power to the ANI0 to ANI5 input circuit. If your application is designed to be changed to backup power, the AVDD pin must be supplied with the same voltage level as the VDD pin, as shown in Figure 11-12. Figure 11-12. AVDD Pin Handling VDD AVDD Main power supply Backup capacitor VSS AVSS (10) AVDD pin input impedance A series resistor string of several ten of k is connected between the AVDD and AVSS pins. Consequently, if the output impedance of the reference voltage supply is high, the reference voltage supply will form a parallel connection with the series resistor string, creating a large reference voltage differential. User's Manual U15075EJ1V0UM00 209 [MEMO] 210 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 12.1 Serial Interface 20 Functions Serial interface 20 has the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. Power consumption is minimized in this mode. (2) Asynchronous serial interface (UART) mode This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex communication. Serial interface 20 contains an UART-dedicated baud rate generator, enabling communication over a wide range of baud rates. It is also possible to define baud rates by dividing the frequency of the clock input to the ASCK20 pin. (3) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission) This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data lines (SI20 and SO20). As it supports simultaneous transmission and reception, 3-wire serial I/O mode requires less processing time for data transmission than asynchronous serial interface mode. Because, in 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB, serial interface 20 can be connected to any device regardless of whether that device is designed for MSB-first or LSB-first transmission. 3-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices. 12.2 Serial Interface 20 Configuration Serial interface 20 includes the following hardware. Table 12-1. Configuration of Serial Interface 20 Item Registers Transmission shift register 20 (TXS20) Reception shift register 20 (RXS20) Reception buffer register 20 (RXB20) Serial operation mode register 20 (CSIM20) Asynchronous serial interface mode register 20 (ASIM20) Asynchronous serial interface status register 20 (ASIS20) Baud rate generator control register 20 (BRGC20) Configuration Control registers User's Manual U15075EJ1V0UM00 211 212 Figure 12-1. Block Diagram of Serial Interface 20 Internal bus Serial operation mode register 20 (CSIM20) CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 Reception buffer register 20 (RXB20) Asynchronous serial interface status register 20 (ASIS20) Asynchronous serial interface mode register 20 (ASIM20) PE20 FE20 OVE20 TXE20 RXE20 PS201 PS200 CL20 SL20 Switching of the first bit Transmission shift register 20 (TXS20) SI20/P25/ RxD20 Port mode register (PM24) Reception shift register 20 (RXS20) Reception shift clock Parity operation Stop bit addition 4 Parity operation Stop bit addition Reception data counter Reception enabled Reception clock Start bit detection Detection clock Reception detected Transmission data counter Transmission shift clock CHAPTER 12 SERIAL INTERFACE 20 Selector Data phase control CSIE20 DAP20 User's Manual U15075EJ1V0UM00 SO20/P24/ TxD20 INTST20 SL20, CL20, PS200, PS201 INTSR20/INTCSI20 Transmission and reception clock control Baud rate generatorNote CSIE20 CSCK20 fX/2 to fX/28 4 SS20/P22 SCK20/P23/ ASCK20 CSIE20 Clock phase control CSCK20 Internal clock output TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) External clock input Internal bus Note See Figure 12-2 for the configuration of the baud rate generator. Figure 12-2. Block Diagram of Baud Rate Generator 20 Reception detection clock Transmission shift clock 1/2 Transmission clock counter fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 SCK20/ASCK20/P23 CHAPTER 12 SERIAL INTERFACE 20 Selector Reception clock counter TXE20 RXE20 CSIE20 Reception detected 4 TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus Selector Reception shift clock 1/2 Selector User's Manual U15075EJ1V0UM00 213 CHAPTER 12 SERIAL INTERFACE 20 (1) Transmission shift register 20 (TXS20) TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit-serially. When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing data to TXS20 triggers transmission. TXS20 can be written with an 8-bit memory manipulation instruction, but cannot be read. RESET input sets TXS20 to FFH. Caution Do not write to TXS20 during transmission. TXS20 and reception buffer register 20 (RXB20) are mapped at the same address, such that any attempt to read from TXS20 results in a value being read from RXB20. (2) Reception shift register 20 (RXS20) RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once one entire byte has been received, RXS20 feeds the reception data to reception buffer register 20 (RXB20). RXS20 cannot be manipulated directly by a program. (3) Reception buffer register 20 (RXB20) RXB20 holds a reception data. A new reception data is transferred from reception shift register 20 (RXS20) every 1-byte data reception. When the data length is seven bits, the reception data is sent to bits 0 to 6 of RXB20, in which the MSB is always fixed to 0. RXB20 can be read with an 8-bit memory manipulation instruction, but cannot be written. RESET input makes RXB20 undefined. Caution RXB20 and transmission shift register 20 (TXS20) are mapped at the same address, such that any attempt to write to RXB20 results in a value being written to TXS20. (4) Transmission controller The transmission controller controls transmission. For example, it adds start, parity, and stop bits to the data in transmission shift register 20 (TXS20), according to the setting of asynchronous serial interface mode register 20 (ASIM20). (5) Reception controller The reception controller controls reception according to the setting of asynchronous serial interface mode register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If an error is detected, asynchronous serial interface status register 20 (ASIS20) is set according to the status of the error. 214 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 12.3 Serial Interface 20 Control Registers Serial interface 20 is controlled by the following registers. * Serial operation mode register 20 (CSIM20) * Asynchronous serial interface mode register 20 (ASIM20) * Asynchronous serial interface status register 20 (ASIS20) * Baud rate generator control register 20 (BRGC20) (1) Serial operation mode register 20 (CSIM20) CSIM20 is used to make the settings related to 3-wire serial I/O mode. CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM20 to 00H. Figure 12-3. Format of Serial Operation Mode Register 20 Symbol <7> CSIM20 6 5 0 4 0 3 2 1 0 Address FF72H After reset 00H R/W R/W CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 1 Operation disabled Operation enabled 3-wire serial I/O mode operation control SSE20 0 1 SS20 pin selection Not used Used Function of SS20/P22 pin Port function 0 1 Communication status Communication enabled Communication enabled Communication disabled DAP20 0 1 3-wire serial I/O mode data phase selection Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 DIR20 0 1 MSB LSB First-bit specification CSCK20 0 1 3-wire serial I/O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator CKP20 0 1 3-wire serial I/O mode clock phase selection Clock is low active, and SCK20 is at high level in the idle state Clock is high active, and SCK20 is at low level in the idle state Cautions 1. Bits 4 and 5 must be set to 0. 2. CSIM20 must be cleared to 00H if UART mode is selected. User's Manual U15075EJ1V0UM00 215 CHAPTER 12 SERIAL INTERFACE 20 (2) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Figure 12-4. Format of Asynchronous Serial Interface Mode Register 20 Symbol <7> ASIM20 <6> 5 4 3 2 SL20 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 RXE20 PS201 PS200 CL20 TXE20 0 1 Transmit operation stop Transmit operation enable Transmit operation control RXE20 0 1 Receive operation stop Receive operation enable Receive operation control PS201 PS200 0 0 1 1 0 1 0 1 No parity Parity bit specification Always add 0 parity at transmission. Parity check is not performed at reception (No parity error is generated). Odd parity Even parity CL20 0 1 7 bits 8 bits Transmit data character length specification SL20 0 1 1 bit 2 bits Transmit data stop bit length Cautions 1. Bits 0 and 1 must be set to 0. 2. If 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. 3. Switch operating modes after halting the serial transmit/receive operation. 216 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 Table 12-2. Serial Interface 20 Operating Mode Settings (1) Operation stop mode CSIM20 PM25 P25 PM24 P24 PM23 P23 First Bit Shift Clock P25/SI20/ RxD20 Pin Function 0 0 0 x x x Note 1 ASIM20 P24/SO20/ TxD20 Pin Function P24 P23/SCK20/ ASCK20 Pin Function P23 TXE20 RXE20 CSIE20 DIR20 CSCK20 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 - - P25 Other than above Setting prohibited (2) 3-wire serial I/O mode CSIM20 PM25 P25 PM24 P24 PM23 P23 First Bit Shift Clock P25/SI20/ RxD20 Pin Function P24/SO20/ TxD20 Pin Function SO20 P23/SCK20/ ASCK20 Pin Function SCK20 ASIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 x Note 2 0 0 1 0 0 x Note 2 0 1 1 x MSB External SI20 clock Note 2 (CMOS output) input 1 0 1 Internal clock SCK20 output SCK20 input SCK20 output 1 1 0 1 x LSB External clock 1 0 1 Internal clock Other than above Setting prohibited (3) Asynchronous serial interface mode CSIM20 PM25 P25 PM24 P24 PM23 P23 First Bit Shift Clock P25/SI20/ RxD20 Pin Function P24/SO20/ TxD20 Pin Function TxD20 P23/SCK20/ ASCK20 Pin Function ASCK20 ASIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 x Note 1 1 0 0 0 0 x Note 1 0 1 1 x LSB External P22 clock (CMOS output) input x Note 1 x Note 1 Internal clock P23 0 1 0 0 0 1 x x Note 1 x Note 1 1 x External RxD20 clock P24 ASCK20 input P23 x Note 1 x Note 1 Internal clock 1 1 0 0 0 1 x 0 1 1 x External clock TxD20 ASCK20 (CMOS output) input x Note 1 x Note 1 Internal clock P23 Other than above Setting prohibited Notes 1. These pins can be used for port functions. 2. When only transmission is used, this pin can be used as P25 (CMOS I/O). Remark x: don't care. User's Manual U15075EJ1V0UM00 217 CHAPTER 12 SERIAL INTERFACE 20 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error, if it occurs while asynchronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. The contents of ASIS20 are undefined in 3-wire serial I/O mode. RESET input sets ASIS20 to 00H. Figure 12-5. Format of Asynchronous Serial Interface Status Register 20 Symbol 7 0 6 0 5 0 4 0 3 0 <2> <1> <0> Address FF71H After reset 00H R/W R ASIS20 PE20 FE20 OVE20 PE20 0 1 No parity error has occurred. Parity error flag A parity error has occurred (when the parity of transmit data does not match). FE20 0 1 No framing error has occurred. Flaming error flag A framing error has occurred (when stop bit is not detected).Note 1 OVE20 0 1 No overrun error has occurred. Overrun error flag An overrun error has occurred.Note 2 (when the next receive operation is completed before the data is read from reception buffer register 20) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit. 2. Be sure to read reception buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error will occur. 218 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (4) Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Figure 12-6. Format of Baud Rate Generator Control Register 20 Symbol BRGC20 7 6 5 4 3 0 2 0 1 0 0 0 Address FF73H After reset 00H R/W R/W TPS203 TPS202 TPS201 TPS200 TPS203 TPS202 TPS201 TPS200 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 fX/24 (625 kHz) (313 kHz) 3-bit counter source clock selection n 1 2 3 4 5 6 7 8 fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) Note External clock input to the ASCK20 pin Setting prohibited - Other than above Note An external clock can be used only in UART mode. Cautions 1. When writing to BRGC00 during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC00 during a communication operation. 2. Be sure not to select n = 1 during operation at fX = 5.0 MHz because the resulting baud rate exceeds the rated range. 3. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: Main system clock oscillation frequency 2. n: Values determined by the settings of TPS200 to TPS203 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U15075EJ1V0UM00 219 CHAPTER 12 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the ASCK20 pin. (a) Generation of baud rate transmit/receive clock form system clock The transmit/receive clock is generated by scaling the system clock. The baud rate of a clock generated from the system clock is estimated by using the following expression. [Baud rate] = fX [Hz] 2n + 1 x 8 fX: Main system clock oscillation frequency n: Values in Figure 12-6, determined by the values of TPS200 to TPS203 (2 n 8) Table 12-3. Example of Relationships Between System Clock and Baud Rate Baud Rate (bps) n BRGC20 Set Value fX = 5.0 MHz 1,200 2,400 4,800 9,600 19,200 38,400 76,800 8 7 6 5 4 3 2 70H 60H 50H 40H 30H 20H 10H 1.73 Error (%) fX = 4.9152 MHz 0 Caution Do not select n = 1 during operation at fX = 5.0 MHz because the resulting baud rate exceeds the rated range. 220 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (b) Generation of baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression. [Baud rate] = fASCK [Hz] 16 fASCK: Frequency of clock input to the ASCK20 pin Table 12-4. Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) Baud Rate (bps) 75 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK20 Pin Input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4 User's Manual U15075EJ1V0UM00 221 CHAPTER 12 SERIAL INTERFACE 20 12.4 Serial Interface 20 Operation Serial interface 20 provides the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode 12.4.1 Operation stop mode In operation stop mode, serial transfer is not executed, thereby reducing the power consumption. P23/SCK20/ASCK20, P24/SO20/TxD20, and P25/SI20/RxD20 pins can be used as normal I/O ports. (1) Register setting Operation stop mode is set by serial operation mode register 20 (CSIM20) and asynchronous serial interface mode register 20 (ASIM20). (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM20 to 00H. Symbol CSIM20 <7> CSIE20 6 SSE20 5 0 4 0 3 DAP20 2 DIR20 1 CSCK20 0 CKP20 Address FF72H After reset 00H R/W R/W The CSIE20 0 1 Operation disabled Operation enabled Operation control in 3-wire serial I/O mode Caution Bits 4 and 5 must be set to 0. 222 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol ASIM20 <7> TXE20 <6> RXE20 5 PS201 4 PS200 3 CL20 2 SL20 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 0 1 Transmit operation stopped Transmit operation enabled Transmit operation control RXE20 0 1 Receive operation stopped Receive operation enabled Receive operation control Caution Bits 0 and 1 must be set to 0. User's Manual U15075EJ1V0UM00 223 CHAPTER 12 SERIAL INTERFACE 20 12.4.2 Asynchronous serial interface (UART) mode In this mode, the one-byte data following the start bit is transmitted/received, enabling full-duplex communication. This device incorporates UART-dedicated baud rate generator that enables communications at the desired baud rate. In addition, the baud rate can also be defined by dividing the clock input to the ASCK20 pin. The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate that complies with the MIDI standard. (1) Register setting UART mode is set by serial operation mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), and baud rate generator control register 20 (BRGC20). 224 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM20 to 00H. Set CSIM20 to 00H when UART mode is selected. Symbol <7> CSIM20 6 5 0 4 0 3 2 1 0 Address FF72H After reset 00H R/W R/W CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 1 Operation disabled Operation enabled 3-wire serial I/O mode operation control SSE20 0 1 SS20 pin selection Not used Used Function of SS20/P22 pin Port function 0 1 Communication status Communication enabled Communication enabled Communication disabled DAP20 0 1 3-wire serial I/O mode data phase selection Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 DIR20 0 1 MSB LSB First-bit specification CSCK20 0 1 3-wire serial I/O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator CKP20 0 1 3-wire serial I/O mode clock phase selection Clock is low active, and SCK20 is high level in the idle state Clock is high active, and SCK20 is low level in the idle state Caution Bits 4 and 5 must be set to 0. User's Manual U15075EJ1V0UM00 225 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. Symbol ASIM20 <7> TXE20 <6> RXE20 5 PS201 4 PS200 3 CL20 2 SL20 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 0 1 Transmit operation stopped Transmit operation enabled Transmit operation control RXE20 0 1 Receive operation stopped Receive operation enabled Receive operation control PS201 0 0 PS200 0 1 No parity Parity bit specification Always add 0 parity at transmission. Parity check is not performed at reception (No parity error is generated). Odd parity Even parity 1 1 0 1 CL20 0 1 7 bits 8 bits Character length specification SL20 0 1 1 bit 2 bits Transmit data stop bit length specification Cautions 1. 2. Bits 0 and 1 must be set to 0. Switch operating modes after halting the serial transmit/receive operation. 226 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (c) Asynchronous serial interface status register 20 (ASIS20) ASIS20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS20 to 00H. Symbol ASIS20 7 0 6 0 5 0 4 0 3 0 <2> PE20 <1> FE20 <0> OVE20 Address FF71H After reset 00H R/W R PE20 0 1 No parity error has occured Parity error flag A parity error has occured (when the parity of transmit data does not match) FE20 0 1 No framing error has occured Framing error flag A framing error has occured (when stop bit is not detected)Note 1 OVE20 0 1 No overrun error has occured Overrun error flag An overrun error has occuredNote 2 (when the next receive operation is completed before data is read from reception buffer register 20) Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface mode register 20 (ASIM20), the stop bit detection at reception is performed with 1 bit. 2. Be sure to read reception buffer register 20 (RXB20) when an overrun error occurs. If not, every time the data is received an overrun error will occur. User's Manual U15075EJ1V0UM00 227 CHAPTER 12 SERIAL INTERFACE 20 (d) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol BRGC20 7 TPS203 6 TPS202 5 TPS201 4 TPS200 3 0 2 0 1 0 0 0 Address FF73H After reset 00H R/W R/W TPS203 0 0 0 0 0 0 0 0 1 TPS202 0 0 0 0 1 1 1 1 0 TPS201 0 0 1 1 0 0 1 1 0 TPS200 0 1 0 1 0 1 0 1 0 fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 fX/26 (156 kHz) (78.1 kHz) 3-bit counter source clock selection n 1 2 3 4 5 6 7 8 - fX/27 (39.1 kHz) fX/28 (19.5 kHz) External clock input to ASCK20 pinNote Setting prohibited Other than above Note Can only be used in the UART mode. Cautions 1. When writing to BRGC20 during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during a communication operation. 2. 3. Be sure not to select n = 1 during operation at fX = 5.0 MHz because the resulting baud rate exceeds the rated range. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: Main system clock oscillation frequency 2. n: Values determined by the settings of TPS200 to TPS203 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz. 228 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the ASCK20 pin. (i) Generation of baud rate transmit/receive clock from system clock The transmit/receive clock is generated by scaling the system clock. The baud rate of a clock generated from the system clock is estimated by using the following expression. [Baud rate] = fX [Hz] 2n + 1 x 8 fX: Main system clock oscillation frequency n: Values in the above table determined by the settings of TPS200 to TPS203 (2 n 8) Table 12-5. Example of Relationships Between System Clock and Baud Rate Baud Rate (bps) n BRGC20 Set Value fX = 5.0 MHz 1,200 2,400 4,800 9,600 19,200 38,400 76,800 8 7 6 5 4 3 2 70H 60H 50H 40H 30H 20H 10H 1.73 Error (%) fX = 4.9152 MHz 0 Caution Do not select n = 1 during operation at fX = 5.0 MHz because the resulting baud rate exceeds the rated range. User's Manual U15075EJ1V0UM00 229 CHAPTER 12 SERIAL INTERFACE 20 (ii) Generation of baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression. [Baud rate] = fASCK [Hz] 16 fASCK: Frequency of clock input to ASCK20 pin Table 12-6. Relationship Between ASCK20 Pin Input Frequency and Baud Rate (When BRGC20 Is Set to 80H) Baud Rate (bps) 75 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK20 Pin Input Frequency (kHz) 1.2 2.4 4.8 9.6 19.2 38.4 76.8 153.6 307.2 500.0 614.4 230 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 12-7. One data frame consists of a start bit, character bits, parity bit, and stop bit(s). The specification of character bit length in one data frame, parity selection, and specification of stop bit length is carried out with asynchronous serial interface mode register 20 (ASIM20). Figure 12-7. Format of Asynchronous Serial Interface Transmit/Receive Data One data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit * Start bits .................. 1 bit * Character bits ........... 7 bits/8 bits * Parity bits.................. Even parity/odd parity/0 parity/no parity * Stop bits.................... 1 bit/2 bits When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". The serial transfer rate is selected by ASIM20 and baud rate generator control register 20 (BRGC20). If a serial data receive error occurs, the receive error contents can be determined by reading the status of asynchronous serial interface status register 20 (ASIS20). User's Manual U15075EJ1V0UM00 231 CHAPTER 12 SERIAL INTERFACE 20 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * At transmission The parity bit is determined so that the number of bits with a value of "1" in the transmit data including the parity bit may be even. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 1 The number of bits with a value of "1" is an even number in transmit data: 0 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is odd, a parity error occurs. (ii) Odd parity * At transmission Conversely to the even parity, the parity bit is determined so that the number of bits with a value of "1" in the transmit data including parity bit may be odd. The parity bit value should be as follows. The number of bits with a value of "1" is an odd number in transmit data: 0 The number of bits with a value of "1" is an even number in transmit data: 1 * At reception The number of bits with a value of "1" in the receive data including parity bit is counted, and if the number is even, a parity error occurs. (iii) 0 parity When transmitting, the parity bit is set to "0" irrespective of the transmit data. At reception, a parity bit check is not performed. irrespective of whether the parity bit is set to "0" or "1". (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error does not occur. Therefore, a parity error does not occur, 232 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (c) Transmission A transmit operation is started by writing transmit data to transmission shift register 20 (TXS20). The start bit, parity bit, and stop bit(s) are added automatically. When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a transmission completion interrupt (INTST20) is generated. Figure 12-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 STOP TxD20 (output) START INTST20 D0 D1 D2 D6 D7 Parity (b) Stop bit length: 2 TxD20 (output) START INTST20 D0 D1 D2 D6 D7 Parity STOP Caution Do not rewrite asynchronous serial interface mode register 20 (ASIM20) during a transmit operation. If the ASIM20 register is rewritten during transmission, subsequent transmission may not be able to be performed (the normal state is restored by RESET input). It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set by INTST20. User's Manual U15075EJ1V0UM00 233 CHAPTER 12 SERIAL INTERFACE 20 (d) Reception When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive operation is enabled and sampling of the RxD20 pin input is performed. RxD20 pin input sampling is performed using the serial clock specified by ASIM20. When the RxD20 pin input becomes low, the 3-bit counter starts counting, and when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. If the RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to reception buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated. If an error occurs, the receive data in which the error occurred is still transferred to RXB20, and INTSR20 is generated. If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are not changed, and INTSR20 is not generated. Figure 12-9. Asynchronous Serial Interface Reception Completion Interrupt Timing STOP RxD20 (input) START INTSR20 D0 D1 D2 D6 D7 Parity Caution Be sure to read reception buffer register 20 (RXB20) even if a receive error occurs. If RXB20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 234 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (e) Receive errors The following three errors may occur during a receive operation: a parity error, framing error, and overrun error. After data reception, an error flag is set in asynchronous serial interface status register 20 (ASIS20). Receive error causes are shown in Table 12-7. It is possible to determine what kind of error occurred during reception by reading the contents of ASIS20 in the reception error interrupt servicing (see Figures 12-9 and 12-10). The contents of ASIS20 are reset (0) by reading reception buffer register 20 (RXB20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 12-7. Receive Error Causes Receive Errors Parity error Framing error Overrun error Cause Transmission-time parity and reception data parity do not match Stop bit not detected Reception of next data is completed before data is read from reception buffer register Figure 12-10. Receive Error Timing (a) Parity error occurrence STOP RxD20 (input) START INTSR20 D0 D1 D2 D6 D7 Parity (b) Framing error or overrun error occurrence STOP RxD20 (input) START INTSR20 D0 D1 D2 D6 D7 Parity Cautions 1. The contents of the ASIS20 register are reset (0) by reading reception buffer register 20 (RXB20) or receiving the next data. To ascertain the error contents, read ASIS20 before reading RXB20. 2. Be sure to read reception buffer register 20 (RXB20) even if a receive error occurs. If RXB20 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. User's Manual U15075EJ1V0UM00 235 CHAPTER 12 SERIAL INTERFACE 20 (3) Cautions related to UART mode (a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during transmission, be sure to set transmission shift register 20 (TXS20) to FFH, then set TXE20 to 1 before executing the next transmission. (b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during reception, reception buffer register 20 (RXB20) and the receive completion interrupt (INTSR20) are as follows. RxD20 pin Parity RXB20 INTSR20 <1> <3> <2> When RXE20 is set to 0 at a time indicated by <1>, RXB20 holds the previous data and INTSR20 is not generated. When RXE20 is set to 0 at a time indicated by <2>, RXB20 renews the data and INTSR20 is not generated. When RXE20 is set to 0 at a time indicated by <3>, RXB20 renews the data and INTSR20 is generated. 236 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 12.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, and 17K Series. Communication is performed using three lines: a serial clock (SCK20), serial output (SO20), and serial input (SI20). (1) Register setting 3-wire serial I/O mode settings are performed using serial operation mode register 20 (CSIM20), asynchronous serial interface mode register 20 (ASIM20), and baud rate generator control register 20 (BRGC20). (a) Serial operation mode register 20 (CSIM20) CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM20 to 00H. Symbol <7> CSIM20 6 5 0 4 0 3 2 1 0 Address FF72H After reset 00H R/W R/W CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 CSIE20 0 1 Operation disabled Operation enabled 3-wire serial I/O mode operation control SSE20 0 1 SS20 pin selection Not used Used Function of SS20/P22 pin Port function 0 1 Communication status Communication enabled Communication enabled Communication disabled DAP20 0 1 3-wire serial I/O mode data phase selection Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 DIR20 0 1 MSB LSB First-bit specification CSCK20 0 1 3-wire serial I/O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator CKP20 0 1 3-wire serial I/O mode clock phase selection Clock is low active, and SCK20 is at high level in the idle state Clock is high active, and SCK20 is at low level in the idle state Caution Bits 4 and 5 must be set to 0. User's Manual U15075EJ1V0UM00 237 CHAPTER 12 SERIAL INTERFACE 20 (b) Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM20 to 00H. When 3-wire serial I/O mode is selected, ASIM20 must be set to 00H. Symbol ASIM20 <7> TXE20 <6> RXE20 5 PS201 4 PS200 3 CL20 2 SL20 1 0 0 0 Address FF70H After reset 00H R/W R/W TXE20 0 1 Transmit operation stopped Transmit operation enabled Transmit operation control RXE20 0 1 Receive operation stopped Receive operation enabled Receive operation control PS201 0 0 PS200 0 1 No parity Parity bit specification Always add 0 parity at transmission. Parity check is not performed at reception (No parity error occurs). Odd parity Even parity 1 1 0 1 CL20 0 1 7 bits 8 bits Transmit data character length specification SL20 0 1 1 bit 2 bits Transmit data stop bit length specification Cautions 1. Bits 0 and 1 must be set to 0. 2. Switch operating modes after halting the serial transmit/receive operation. 238 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 (c) Baud rate generator control register 20 (BRGC20) BRGC20 is set with an 8-bit memory manipulation instruction. RESET input sets BRGC20 to 00H. Symbol BRGC20 7 TPS203 6 TPS202 5 TPS201 4 TPS200 3 0 2 0 1 0 0 0 Address FF73H After reset 00H R/W R/W TPS203 0 0 0 0 0 0 0 0 TPS202 0 0 0 0 1 1 1 1 TPS201 0 0 1 1 0 0 1 1 TPS200 0 1 0 1 0 1 0 1 fX/2 (2.5 MHz) 3-bit counter source clock selection n 1 2 3 4 5 6 7 8 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 fX/26 fX/27 (156 kHz) (78.1 kHz) (39.1 kHz) fX/28 (19.5 kHz) Setting prohibited Other than above Cautions 1. When writing to BRGC20 during a communication operation, the baud rate generator output is disrupted and communications cannot be performed normally. Be sure not to write to BRGC20 during a communication operation. 2. Be sure not to select n = 1 during operation at fX = 5.0 MHz because the resulting baud rate exceeds the rated range. 3. When the external input clock is selected, set port mode register 2 (PM2) to input mode. Remarks 1. fX: 2. n: Main system clock oscillation frequency Values determined by the settings of TPS200 to TPS203 (1 n 8) 3. The parenthesized values apply to operation at fX = 5.0 MHz. If the internal clock is used as the serial clock for 3-wire serial I/O mode, set bits TPS200 to TPS203 to set the frequency of the serial clock. To obtain the frequency to be set, use the following expression. When an external clock is used, setting BRGC20 is not necessary. Serial clock frequency = fX [Hz] 2n + 1 fX: Main system clock oscillation frequency n: Values in the above table determined by the settings of TPS200 to TPS203 (1 n 8) User's Manual U15075EJ1V0UM00 239 CHAPTER 12 SERIAL INTERFACE 20 (2) Communication operation In 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. transmitted/received bit by bit in synchronization with the serial clock. Transmission shift register (TXS20/SIO20) and reception shift register (RXS20) shift operations are performed in synchronization with the fall of the serial clock (SCK20). Then transmit data is held in the SO20 latch and output from the SO20 pin. Also, receive data input to the SI20 pin is latched in the reception buffer register (RXB20/SIO20) on the rise of SCK20. At the end of an 8-bit transfer, the operation of TXS20/SIO20 and RXS20 stops automatically, and the interrupt request signal (INTCSI20) is generated. Figure 12-11. 3-Wire Serial I/O Mode Timing (1/7) (i) Master operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) Data is SIO20 write SCK20 1 2 3 4 5 6 7 8 SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 Note The value of the last bit previously output is output. 240 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (2/7) (ii) Slave operation timing (when DAP20 = 0, CKP20 = 0, SSE20 = 0) SIO20 write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The value of the last bit previously output is output. (iii) Slave operation (when DAP20 = 0, CKP20 = 0, SSE20 = 1) SS20 SIO20 write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z Note 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 Hi-Z INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. User's Manual U15075EJ1V0UM00 241 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (3/7) (iv) Master operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 (v) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 SIO20 write (master)Note SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. 242 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (4/7) (vi) Slave operation (when DAP20 = 0, CKP20 = 1, SSE20 = 1) SS20 SIO20 write SCK20 SIO20 write (master)Note 1 SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first rising edge of SCK20. Make sure that the master outputs the first bit before the first rising of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. (vii) Master operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 write SCK20 1 2 3 4 5 6 7 8 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 User's Manual U15075EJ1V0UM00 243 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (5/7) (viii) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 0) SIO20 write SCK20 SIO20 write (master)Note SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. (ix) Slave operation (when DAP20 = 1, CKP20 = 0, SSE20 = 1) SS20 SIO20 write SCK20 SIO20 write (master)Note 1 SI20 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Note 2 Hi-Z INTCSI20 Notes 1. The data of SI20 is loaded at the first falling edge of SCK20. Make sure that the master outputs the first bit before the first falling of SCK20. 2. SO20 is high until SS20 rises after completion of DO0 output. When SS20 is high, SO20 is in a high-impedance state. 244 User's Manual U15075EJ1V0UM00 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (6/7) (x) Master operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 1 2 3 4 5 6 7 8 SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 INTCSI20 Note The value of the last bit previously output is output. (xi) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 0) SIO20 write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Note DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSI20 Note The value of the last bit previously output is output. User's Manual U15075EJ1V0UM00 245 CHAPTER 12 SERIAL INTERFACE 20 Figure 12-11. 3-Wire Serial I/O Mode Timing (7/7) (xii) Slave operation (when DAP20 = 1, CKP20 = 1, SSE20 = 1) SS20 SIO20 write SCK20 1 2 3 4 5 6 7 8 SI20 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO20 Hi-Z Note 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 Hi-Z INTCSI20 Notes 1. The value of the last bit previously output is output. 2. DO0 is output until SS20 rises. When SS20 is high, SO20 is in a high-impedance state. (3) Transfer start Serial transfer is started by setting transfer data to the transmission shift register (TXS20/SIO20) when the following two conditions are satisfied. * Bit 7 (CSIE20) of serial operation mode register 20 (CSIM20) = 1 * Internal serial clock is stopped or SCK20 is high after 8-bit serial transfer. Caution If CSIE20 is set to "1" after data is written to TXS20/SIO20, transfer does not start. Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (INTCSI20). 246 User's Manual U15075EJ1V0UM00 CHAPTER 13 LCD CONTROLLER/DRIVER 13.1 LCD Controller/Driver Functions The functions of the LCD controller/driver of the PD789426, 789436, 789446, and 789456 Subseries are as follows. (1) (2) Automatic output of segment and common signals based on automatic display data memory read Two different display modes: * 1/3 duty (1/3 bias) * 1/4 duty (1/3 bias) (3) (4) Four different frame frequencies, selectable in each display mode Operation with a subsystem clock Table 13-1 lists the maximum number of pixels that can be displayed in each display mode. Table 13-1. Number of Segment Outputs and Maximum Number of Pixels Bias Method Time Slots Common Signals Used COM0 to COM2 COM0 to COM3 COM0 to COM2 COM0 to COM3 15 Maximum Number of Segments 5 Maximum Number of Pixels 15 (5 segments x 3 commons) 20 (5 segments x 4 commons) 45 (15 segments x 3 commons) 60 (15 segments x 4 commons) PD789426, 789436 Subseries PD789446, 789456 Subseries 1/3 3 4 3 4 13.2 LCD Controller/Driver Configuration The LCD controller/driver includes the following hardware. Table 13-2. Configuration of LCD Controller/Driver Item Display outputs Segment signals: Configuration 5 (PD789426 and 789436 Subseries) 15 (PD789446 and 789456 Subseries) Common signals: 4 (COM0 to COM3) LCD display mode register 0 (LCDM0) LCD clock control register 0 (LCDC0) LCD voltage amplification control register 0 (LCDVA0) Control registers User's Manual U15075EJ1V0UM00 247 Selector 248 Figure 13-1. Block Diagram of LCD Controller/Driver Internal bus LCD clock control register 0 (LCDC0) LCDC03 LCDC02 LCDC01 LCDC00 LCD display mode register 0 (LCDM0) LCDON0 VAON0 LIPS0 LCDM02 LCDM01 LCDM00 LCD voltage amplification control register 0 (LCDVA0) FA00H GAIN 76543210 Display data memory FA04H (FA0EH)Note 76543210 2 2 3 CHAPTER 13 LCD CONTROLLER/DRIVER fX/25 fX/26 fX/27 fXT fLCD fCLK 26 Prescaler fCLK 27 fCLK 28 fCLK 29 LCD LCDCL clock selector Voltage amplifier Timing controller LCDON0 3210 Selector LCDON0 3210 Selector User's Manual U15075EJ1V0UM00 LCD drive voltage controller Common driver Segment driver Segment driver VLC2 VLC1 VLC0 COM0 COM1 COM2 COM3 S0 S4 (S14) Note The parenthesized values apply to the PD789446 and 789456 Subseries. CHAPTER 13 LCD CONTROLLER/DRIVER 13.3 Registers Controlling LCD Controller/Driver * LCD display mode register 0 (LCDM0) * LCD clock control register 0 (LCDC0) * LCD voltage amplification control register 0 (LCDVA0) (1) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display operation. It also specifies the operation mode, LCD drive power supply, and display mode. LCDM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDM0 to 00H. User's Manual U15075EJ1V0UM00 249 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-2. Format of LCD Display Mode Register 0 Symbol LCDM0 <7> <6> 5 0 <4> LIPS0 3 0 2 0 1 0 0 LCDM00 Address FFB0H After reset 00H R/W R/W LCDON0 VAON0 LCDON0 0 1 Display off Display on LCD display enable/disable VAON0 0 1 LCD controller/driver operation modeNote No internal voltage amplification (Normal operation) Internal voltage amplification enabled (Low-voltage operation) LIPS0 0 1 Segment pin/common pin output control bitNote Output ground level to segment/common pin Output deselect level to segment pin and LCD waveform to common pin LCDM00 LCD controller/driver display mode selection Number of time slices Bias mode 1/3 1/3 0 1 4 3 Note When the LCD display panel is not used, the VAON0 and LIPS0 must be set to 0 to reduce power consumption. Cautions 1. Bits 1 to 3 and 5 must be set to 0. 2. When operating VAON0, follow the procedure described below. A. To stop voltage amplification after switching display status from on to off: 1) Set to display off status by setting LCDON0 = 0. 2) Disable outputs of all the segment buffers and common buffers by setting LIPS0 = 0. 3) Stop voltage amplification by setting VAON0= 0. B. To stop voltage amplification during display on status: Setting prohibited. Be sure to stop voltage amplification after setting display off. C. To set display on from voltage amplification stop status: 1) Start voltage amplification by setting VAON0 = 1, then wait for about 500 ms. 2) Set all the segment buffers and common buffers to non-display output status by setting LIPS0 = 1. 3) Set display on by setting LCDON0 = 1. 250 User's Manual U15075EJ1V0UM00 CHAPTER 13 LCD CONTROLLER/DRIVER (2) LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD clock and frame frequency. LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC0 to 00H. Figure 13-3. Format of LCD Clock Control Register 0 Symbol LCDC0 7 0 6 0 5 0 4 0 3 2 1 0 Address FFB2H After reset 00H R/W R/W LCDC03 LCDC02 LCDC01 LCDC00 LCDC03 LCDC02 0 0 1 1 0 1 0 1 fXT (32.768 kHz) Internal clock (fLCD) selectionNote fX/25 (156.3 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) LCDC01 LCDC00 0 0 1 1 0 1 0 1 fLCD/2 6 LCD clock (LCDCL) selection fLCD/27 fLCD/28 fLCD/29 Note Specify an internal clock (fLCD) frequency of at least 32 kHz. Cautions 1. Bits 4 to 7 must be set to 0. 2. Before changing the LCDC0 setting, be sure to stop voltage amplification (VAON0 = 0). 3. Set the frame frequency to 128 Hz or lower. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. Table 13-3 lists the frame frequencies used when fXT (32.768 kHz) is supplied to the internal clock (fCLK1). Table 13-3. Frame Frequencies (Hz) LCD Clock (fLCD) Display Duty Ratio 1/3 1/4 fXT/2 (64 Hz) 21 16 9 fXT/2 (128 Hz) 43 32 8 fXT/2 (256 Hz) 85 64 7 fXT/2 (512 Hz) 171 Note 6 128 Note This setting is prohibited because it causes the frame frequency to exceed 128 Hz. User's Manual U15075EJ1V0UM00 251 CHAPTER 13 LCD CONTROLLER/DRIVER (3) LCD voltage amplification control register 0 (LCDVA0) LCDVA0 controls the voltage amplification level during the voltage amplifier operation. Figure 13-4. Format of LCD Voltage Amplification Control Register 0 Symbol LCDVA0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> GAIN Address FFB3H After reset 00H R/W R/W GAIN 0 1 Reference voltage (VLC2) level selectionNote 1.5 times (specification of the LCD panel used is 4.5 V.) 1.0 times (specification of the LCD panel used is 3 V.) Note Select the settings according to the specifications of the LCD panel that is used. Caution Remark Before changing the LCDVA0 setting, be sure to stop voltage amplification (VAON0 = 0). The TYP. value is indicated as the reference voltage (VLC2) value. 252 User's Manual U15075EJ1V0UM00 CHAPTER 13 LCD CONTROLLER/DRIVER 13.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the frame frequency using LCD clock control register 0 (LCDC0). <2> Set the voltage amplification level using LCD voltage amplification control register 0 (LCDVA0). GAIN = 0: VLC0 = 4.5 V, VLC1 = 3 V, VLC2 = 1. 5 V GAIN = 1: VLC0 = 3 V, VLC1 = 2 V, VLC2 = 1 V <3> Set the time division using LCDM00 (bit 0 of LCD display mode register 0 (LCDM0)). <4> Enable voltage amplification by setting VAON0 (bit 6 of LCDM0) (VAON0 = 1). <5> Wait for 500 ms or more after setting VAON0. <6> Set LIPS0 (bit 4 of LCDM0) (LIPS0 = 1) and output the deselect potential. <7> Start output corresponding to each data memory by setting LCDON0 (bit 7 of LCDM0) (LCDON0 =1). 13.5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA0EH. Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller/driver. Figure 13-5 shows the relationship between the contents of the LCD display data memory and the segment/common outputs. That part of the display data memory which is not used for display can be used as ordinary RAM. Figure 13-5. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs (PD789446, 789456 Subseries) Address FA0EH FA0DH FA0CH b7 b6 b5 b4 b3 b2 b1 b0 S14 S13 S12 S11 FA02H FA01H FA00H S2 S1 S0 COM3 COM2 COM1 COM0 Caution No memory has been installed as the higher 4 bits of the LCD display data memory. Be sure to set 0 to them. User's Manual U15075EJ1V0UM00 253 CHAPTER 13 LCD CONTROLLER/DRIVER 13.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). It turns off when the potential difference becomes lower than VLCD. Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it. To avoid this problem, this LCD panel is driven with AC voltage. (1) Common signals Each common signal is selected sequentially according to a specified number of time slots at the timing listed in Table 13-4. In the static display mode, the same signal is output to COM0 to COM3 in common. In the three-time slot mode, keep the COM3 pin open. Table 13-4. COM Signals COM Signal Number of Time Slots Three-time slot mode Four-time slot mode Open COM0 COM1 COM2 COM3 (2) Segment signals The segment signals correspond to LCD display data memory. Bits 0, 1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If the contents of each bit are 1, it is converted to the select voltage, and if 0, it is converted to the deselect voltage. The conversion results are output to the segment pins. Check, with the information given above, what combination of the front-surface electrodes (corresponding to the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display patterns in the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one basis. Bit 3 of the LCD display data memory is not used for LCD display in the three-time slot mode. So this bit can be used for purposes other than display. LCD display data memory bits 4 to 7 are fixed to 0. (3) Output waveforms of common and segment signals Voltages listed in Table 13-5 are output as common and segment signals. When both common and segment signals are at the select voltage, a display-on voltage of VLCD is obtained. The other combinations of the signals correspond to the display-off voltage. Table 13-5. LCD Drive Voltage Segment Signal Select Signal Level VSS0/VLC0 VLC0/VSS0 VLC2/VLC1 -VLCD/+VLCD - 1 1 VLCD/+ VLCD 3 3 Deselect Signal Level VLC1/VLC2 1 1 - VLCD/+ VLCD 3 3 1 1 - VLCD/+ VLCD 3 3 Common Signal Select signal level Deselect signal level 254 User's Manual U15075EJ1V0UM00 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-6 shows the common signal waveforms, and Figure 13-7 shows the voltages and phases of the common and segment signals. Figure 13-6. Common Signal Waveforms VLC0 COMn (Three-time slot mode) TF = 3 x T VLC0 COMn (Four-time slot mode) TF = 4 x T VLC1 VLC2 VSS VLCD VLC1 VLC2 VSS VLCD T: One LCD clock period TF: Frame frequency Figure 13-7. Voltages and Phases of Common and Segment Signals Select Deselect VLC0 Common signal VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS T T VLCD Segment signal VLCD T: One LCD clock period User's Manual U15075EJ1V0UM00 255 CHAPTER 13 LCD CONTROLLER/DRIVER 13.7 Display Modes 13.7.1 Three-time slot display example Figure 13-9 shows how the 5-digit LCD panel having the display pattern shown in Figure 13-8 is connected to the segment signals (S0 to S14) and the common signals (COM0 to COM2) of the PD789446 or PD789456 Subseries chip. This example displays data "123.45" in the LCD panel. The contents of the display data memory (addresses FA00H to FA0EH) correspond to this display. The following description focuses on numeral "3." ( .) displayed in the third digit. To display "3." in the LCD panel, it is necessary to apply the select or deselect voltage to the S6 to S8 pins according to Table 13-6 at the timing of the common signals COM0 to COM2. Table 13-6. Select and Deselect Voltages (COM0 to COM2) Segment Common COM0 COM1 COM2 Select Select Select Select Select Select Deselect Deselect - S6 S7 S8 According to Table 13-6, it is determined that the display data memory location (FA06H) that corresponds to S6 must contain x111. Figure 13-10 shows examples of LCD drive waveforms between the S6 signal and each common signal. When the select voltage is applied to S6 at the timing of COM1 or COM2, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. Figure 13-8. Three-Time Slot LCD Display Pattern and Electrode Connections S3n+1 COM0 S3n+2 Remark n = 0 to 4 ,, ,, ,, , ,, , S3n ,,, ,, ,,, ,, ,, ,, ,, ,, ,, COM2 COM1 256 User's Manual U15075EJ1V0UM00 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-9. Example of Connecting Three-Time Slot LCD Panel Timing strobe COM 3 COM 2 COM 1 COM 0 Bit 1 Bit 2 Bit 0 Bit 3 Open 001011011101110 001110011011011 x' 0 0 x' 1 0 x' 1 1 x' 0 0 x' 1 0 xxxxxxxxxxxxxxx FA00H 1 2 3 Data memory address S0 S1 S2 S3 S4 S6 S7 S8 S9 S 10 S 11 S 12 S 13 S 14 LCD panel 4 5 6 7 8 9 A B C D E S5 x': Can be used to store any data because there is no corresponding segment in the LCD panel. x: Can always be used to store any data because of the three-time slot mode being used. User's Manual U15075EJ1V0UM00 257 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-10. Three-Time Slot LCD Drive Waveform Examples TF VLC0 COM0 VLC1 VLC2 VSS0 VLC0 COM1 VLC1 VLC2 VSS0 VLC0 COM2 VLC1 VLC2 VSS0 VLC0 S6 VLC1 VLC2 VSS0 +VLCD +1/3VLCD COM0-S6 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM1-S6 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM2-S6 0 -1/3VLCD -VLCD 258 User's Manual U15075EJ1V0UM00 CHAPTER 13 LCD CONTROLLER/DRIVER 13.7.2 Four-time slot display example Figure 13-12 shows how the 7-digit LCD panel having the display pattern shown in Figure 13-11 is connected to the segment signals (S0 to S14) and the common signals (COM0 to COM3) of the PD789446 or PD789456 Subseries chip. This example displays data "123456.7" in the LCD panel. The contents of the display data memory (addresses FA00H to FA0EH) correspond to this display. The following description focuses on numeral "6." ( timing of the common signals COM0 to COM3. Table 13-7. Select and Deselect Voltages (COM0 to COM3) Segment Common COM0 COM1 COM2 COM3 Select Deselect Select Select Select Select Select Select S2 S3 ) displayed in the seventh digit. To display "6." in the LCD panel, it is necessary to apply the select or deselect voltage to the S2 and S3 pins according to Table 13-7 at the According to Table 13-7, it is determined that the display data memory location (FA02H) that corresponds to S2 must contain 1101. Figure 13-13 shows examples of LCD drive waveforms between the S2 signal and the COM0 or COM1 signal (the waveforms for COM2 and COM3 have been left out from the drawing). When the select voltage is applied to S2 at the timing of COM0, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. Figure 13-11. Four-Time Slot LCD Display Pattern and Electrode Connections S2n Remark , ,,, , S2n+1 COM0 COM1 COM2 COM3 n = 0 to 7 User's Manual U15075EJ1V0UM00 259 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-12. Example of Connecting Four-Time Slot LCD Panel COM 3 Timing strobe COM 2 COM 1 COM 0 Bit 0 Bit 1 Bit 2 Bit 3 1 1 FA00H 1 2 3 1 0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 0 0 1 1 1 0 0 1 1 Data memory address 1 0 5 6 7 8 9 A B C D 1 0 1 1 1 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 260 0 0 0 1 0 1 0 0 User's Manual U15075EJ1V0UM00 LCD panel 4 1 1 0 1 1 1 0 0 1 0 1 1 0 CHAPTER 13 LCD CONTROLLER/DRIVER Figure 13-13. Four-Time Slot LCD Drive Waveform Examples TF VLC0 COM0 VLC1 VLC2 VSS VLC0 COM1 VLC1 VLC2 VSS VLC0 COM2 VLC1 VLC2 VSS VLC0 COM3 VLC1 VLC2 VSS VLC0 S2 VLC1 VLC2 VSS +VLCD +1/3VLCD COM0-S2 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM1-S2 0 -1/3VLCD -VLCD User's Manual U15075EJ1V0UM00 261 [MEMO] 262 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS 14.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) Maskable interrupt This interrupt undergoes mask control. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in Table 14-1. A standby release signal is generated. 5 external and 9 internal interrupt sources are incorporated as maskable interrupts. 14.2 Interrupt Sources and Configuration A total of 15 non-maskable and maskable interrupts are incorporated as interrupt sources (see Table 14-1). User's Manual U15075EJ1V0UM00 263 CHAPTER 14 INTERRUPT FUNCTIONS Table 14-1. Interrupt Source List Interrupt Type Priority Note 1 Interrupt Source Name Trigger Internal/ External Vector Table Address Basic Configuration Type Note 2 Non-maskable - INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection Internal 0004H (A) Maskable 0 INTWDT (B) 1 2 3 4 5 INTP0 INTP1 INTP2 INTP3 INTSR20 External 0006H 0008H 000AH 000CH (C) End of serial interface 20 UART reception End of serial interface 20 3-wire SIO transfer reception End of serial interface 20 UART transmission Interval timer interrupt Generation of match signal of 16-bit timer 90 Generation of match signal of 8-bit timer 50 Generation of match signal of 8-bit timer 60 End of A/D conversion signal Watch timer interrupt Key return signal detection Internal 000EH (B) INTCSI20 6 INTST20 0012H 7 8 INTWTI INTTM90 0014H 0016H 9 INTTM50 0018H 10 INTTM60 001AH 11 12 13 INTAD0 INTWT INTKR00 001CH 001EH External 0020H (C) Notes 1. Priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and 13 is the lowest order. 2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 14-1. Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable and maskable interrupts (internal). Either one (but not both) should be selected for actual use. 264 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Interrupt request Vector table address generator Standby release signal (B) Internal maskable interrupt Internal bus MK IE Interrupt request IF Vector table address generator Standby release signal (C) External maskable interrupt Internal bus INTM0, INTM1, KRM00 MK IE Interrupt request Edge detector IF Vector table address generator Standby release signal INTM0: INTM1: KRM00: IF: IE: MK: External interrupt mode register 0 External interrupt mode register 1 Key return mode register 00 Interrupt request flag Interrupt enable flag Interrupt mask flag User's Manual U15075EJ1V0UM00 265 CHAPTER 14 INTERRUPT FUNCTIONS 14.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions. * Interrupt request flag registers 0, 1 (IF0 and IF1) * Interrupt mask flag registers 0, 1 (MK0 and MK1) * External interrupt mode registers 0, 1 (INTM0 and INTM1) * Program status word (PSW) * Key return mode register 00 (KRM00) Table 14-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. Table 14-2. Flags Corresponding to Interrupt Request Signal Name Interrupt Request Signal Name INTWDT INTP0 INTP1 INTP2 INTP3 INTSR20/INTCSI20 INTST20 INTWTI INTTM90 INTTM50 INTTM60 INTAD0 INTWT INTKR00 WDTIF PIF0 PIF1 PIF2 PIF3 SRIF20 STIF20 WTIIF TMIF90 TMIF50 TMIF60 ADIF0 WTIF KRIF00 Interrupt Request Flag WDTMK PMK0 PMK1 PMK2 PMK3 SRMK20 STMK20 WTIMK TMMK90 TMMK50 TMMK60 ADMK0 WTMK KRMK00 Interrupt Mask Flag 266 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS (1) Interrupt request flag registers 0, 1 (IF0 and IF1) The interrupt request flag is set (1) when the corresponding interrupt request is generated or an instruction is executed. It is cleared (0) when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input. IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets IF0 and IF1 to 00H. Figure 14-2. Format of Interrupt Request Flag Registers Symbol <7> IF0 STIF20 7 IF1 0 6 0 <6> <5> <4> <3> PIF2 <3> <2> PIF1 <2> <1> <0> Address FFE0H After reset 00H R/W R/W SRIF20 PIF3 <5> <4> PIF0 WDTIF <1> <0> KRIF00 WTIF ADIF0 TMIF40 TMIF30 TMIF20 WTIIF FFE1H 00H R/W XXIFX 0 1 Interrupt request flag No interrupt request signal is generated Interrupt request signal is generated; Interrupt request state Cautions 1. Bit 7 of IF1 and bit 6 of IF0 must be set to 0. 2. The WDTIF flag is R/W enabled only when a watchdog timer is used as an interval timer. If the watchdog timer mode 1 or 2 is used, set the WDTIF flag to 0. 3. Because port 3 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. User's Manual U15075EJ1V0UM00 267 CHAPTER 14 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers 0, 1 (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 14-3. Format of Interrupt Mask Flag Registers Symbol MK0 <7> STMK20 7 6 1 <6> <5> <4> <3> <2> <1> <0> Address FFE4H After reset FFH R/W R/W SRMK20 PMK3 PMK2 PMK1 PMK0 WDTMK <5> <4> <3> <2> <1> <0> MK1 1 KRMK00 WTMK ADMK0 TMMK40 TMMK30 TMMK20 WTIMK FFE5H FFH R/W XXMK 0 1 Interrupt servicing enabled Interrupt servicing disabled Interrupt servicing control Cautions 1. Bits 7 of MK1 and bit 6 of MK0 must be set to 1. 2. If the WDTMK flag is read when the watchdog timer is used in watchdog timer mode 1 or 2, its value becomes undefined. 3. Because port 3 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 268 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) This register is used to specify a valid edge for INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Figure 14-4. Format of External Interrupt Mode Register 0 Symbol INTM0 7 6 5 4 3 2 1 0 0 0 Address FFECH After reset 00H R/W R/W ES21 ES20 ES11 ES10 ES01 ES00 ES21 ES20 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP2 valid edge selection ES11 ES10 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 valid edge selection ES01 ES00 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP0 valid edge selection Cautions 1. Bits 0 and 1 must be set to 0. 2. Before setting the INTM0 register, be sure to set the relevant interrupt mask flag to 1 to disable interrupts. After that, clear (0) the interrupt request flag, then set the interrupt mask flag to 0 to enable interrupts. User's Manual U15075EJ1V0UM00 269 CHAPTER 14 INTERRUPT FUNCTIONS (4) External interrupt mode register 1 (INTM1) INTM1 is used to specify a valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 14-5. Format of External Interrupt Mode Register 1 Symbol INTM1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFEDH After reset 00H R/W R/W ES31 ES30 ES31 ES30 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges INTP3 valid edge selection Cautions 1. Bits 2 to 7 must be set to 0. 2. Before setting INTM1, set PMK3 to 1 to disable interrupts. After that, clear (0) PIF3, then set PMK3 to 0 to enable interrupts. (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved into a stack, and the IE flag is reset to 0. RESET input sets PSW to 02H. Figure 14-6. Configuration of Program Status Word Symbol PSW 7 IE 6 Z 5 0 4 AC 3 0 2 0 1 1 0 CY After reset 02H Used when normal instruction is executed IE 0 1 Disabled Enabled Interrupt acknowledgement enabled/disabled 270 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS (6) Key return mode register 00 (KRM00) This register sets the pin that detects a key return signal (falling edge of port 0). KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM00 to 00H. Figure 14-7. Format of Key Return Mode Register 00 Symbol KRM00 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 KRM000 Address FFF5H After reset 00H R/W R/W KRM000 0 1 No detection Key return signal detection control Detection (detecting falling edge of port 0) Cautions 1. Bits 1 to 7 must be set to 0. 2. Before setting KRM00, always set bit 6 of MK1 (KRMK00 = 1) to disable interrupts. After setting KRM00, clear KRMK00 after clearing bit 6 of IF1 (KRIF00 = 0) to enable interrupts. 3. When P00 to P03 are in input mode, on-chip pull-up resistors are connected to P00 to P03 by the setting of KRM000. After switching to output mode, the on-chip pull-up resistors are cut off. However, key return signal detection continues. Figure 14-8. Block Diagram of Falling Edge Detector Key return mode register 00 (KRM00) Note P00/KR0 P01/KR1 P02/KR2 P03/KR3 KRMK00 Standby release signal Selector Falling edge detector KRIF00 set signal Note Selector that selects the pin used for falling edge input User's Manual U15075EJ1V0UM00 271 CHAPTER 14 INTERRUPT FUNCTIONS 14.4 Interrupt Servicing Operation 14.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Figure 14-9 shows the flow from non-maskable interrupt request generation to acknowledgement, Figure 14-10 shows the timing of non-maskable interrupt acknowledgement, and Figure 14-11 shows the acknowledgement operation when a number of non-maskable interrupts are generated. Caution During non-maskable interrupt service program execution, do not input another non-maskable interrupt request; if it is input, the service program will be interrupted and the new nonmaskable interrupt request will be acknowledged. 272 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-9. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Yes No Interval timer WDT overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Yes Interrupt request is generated No Reset processing Interrupt servicing starts WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 14-10. Timing of Non-Maskable Interrupt Request Acknowledgment CPU processing Instruction Instruction Saving PSW and PC, and jump to interrupt servicing Interrupt servicing program WDTIF Figure 14-11. Non-Maskable Interrupt Request Acknowledgment Main routine First interrupt servicing NMI request (first) NMI request (second) Second interrupt servicing User's Manual U15075EJ1V0UM00 273 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 14-3. Refer to Figures 14-13 and 14-14 for the timing of interrupt request acknowledgement. Table 14-3. Time from Generation of Maskable Interrupt Request to Servicing Minimum Time 9 clocks Maximum Time 19 clocks Note Note The wait time is maximum when an interrupt request is generated immediately before BT or BF instruction. Remark 1 clock: 1 fCPU (fCPU: CPU clock) When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. A pending interrupt is acknowledged when the status where it can be acknowledged is set. Figure 14-12 shows the algorithm of interrupt request acknowledgement. When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. Figure 14-12. Interrupt Request Acknowledgment Program Algorithm Start No xxIF = 1 ? Yes (Interrupt request generated) No xxMK = 0 ? Yes No IE = 1 ? Interrupt request pending Yes Vectored interrupt servicing Interrupt request pending xxIF: Interrupt request flag xxMK: Interrupt mask flag IE: Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable) User's Manual U15075EJ1V0UM00 274 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r) 8 clocks Clock CPU MOV A, r Saving PSW and PC, and jump to interrupt servicing Interrupt servicing program Interrupt If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n - 1, interrupt request acknowledgment processing will start following the completion of the instruction under execution. Figure 14-13 shows an example using the 8-bit data transfer instruction MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of MOV A, r. Figure 14-14. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final Clock Under Execution) 8 clocks Clock CPU NOP MOV A, r Saving PSW and PC, and jump to interrupt servicing Interrupt servicing program Interrupt If the interrupt request flag (XXIF) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after execution of the next instruction is complete. Figure 14-14 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock instruction). In this case, the interrupt request will be processed after execution of MOV A, r, which follows NOP, is complete. Caution When interrupt request flag registers 0 and 1 (IF0 and IF1), or interrupt mask flag registers 0 and 1 (MK0 and MK1) are being accessed, interrupt requests will be held pending. 14.4.3 Multiple interrupt servicing Multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced, can be serviced using the priority order. If multiple interrupts are generated at the same time, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to Table 14-1). User's Manual U15075EJ1V0UM00 275 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-15. Example of Multiple Interrupts Example 1. Acknowledging multiple interrupts Main servicing INTxx servicing INTyy servicing EI IE = 0 EI IE = 0 INTxx INTyy RETI RETI The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are performed. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is enabled. Example 2. Multiple interrupts are not performed because interrupts are disabled Main servicing INTxx servicing INTyy servicing EI IE = 0 INTyy RETI INTyy is held pending INTxx IE = 0 RETI Because interrupt requests are disabled (the EI instruction has not been issued) in the interrupt INTxx servicing, the interrupt request INTyy is not acknowledged and multiple interrupts are not performed. INTyy is held pending and is acknowledged after INTxx servicing is completed. IE = 0: Interrupt requests disabled 276 User's Manual U15075EJ1V0UM00 CHAPTER 14 INTERRUPT FUNCTIONS 14.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows. * Instructions that manipulate interrupt request flag registers 0, 1 (IF0 and IF1) * Instructions that manipulate interrupt mask flag registers 0, 1 (MK0 and MK1) User's Manual U15075EJ1V0UM00 277 [MEMO] 278 User's Manual U15075EJ1V0UM00 CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is to reduce the power consumption of the system and can be effected in the following two modes: (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this mode. The data memory can be retained at the low voltage (VDD = 1.8 V). Therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained. Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction. User's Manual U15075EJ1V0UM00 279 CHAPTER 15 STANDBY FUNCTION 15.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 215/fX, not 217/fX, after RESET input. Figure 15-1. Format of Oscillation Stabilization Time Select Register Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFAH After reset 04H R/W R/W OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 0 0 1 0 1 0 0 0 0 212/fX (819 s) 215/fX (6.55 ms) 217/fX (26.2 ms) Setting prohibited Oscillation stabilization time selection Other than above Caution The wait time after the STOP mode is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of whether STOP mode is released by RESET input or by interrupt generation. STOP mode release X1 pin voltage waveform VSS a Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 280 User's Manual U15075EJ1V0UM00 CHAPTER 15 STANDBY FUNCTION 15.2 Standby Function Operation 15.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 15-1. HALT Mode Operating Status Item HALT Mode Operation Status While The Main System Clock Is Running While the subsystem clock is running While the subsystem clock is not running HALT Mode Operation Status While The Subsystem Clock Is Running While the main system clock is running While the main system clock is not running Oscillation stopped Main system clock CPU Port (output latch) 16-bit timer 8-bit timer TM50 TM60 Watch timer Watchdog timer Serial interface A/D converter LCD controller/driver External interrupt Oscillation enabled Operation stopped Remains in the state existing before the selection of HALT mode. Operation enabled Operation enabled Operation stopped Operation enabled Note 1 Operation enabled Operation enabled Operation enabled Operation enabled Operation stopped Operation enabled Operation enabled Note 6 Note 2 Operation enabled Note 3 Operation enabled Operation stopped Operation enabled Note 4 Operation stopped Note 5 Operation enabled Note 3 Operation enabled Operation enabled Note 4 Notes 1. Operation is enabled only when input signal from timer 60 (timer 60 operation is enabled) is selected as the count clock. 2. Operation is enabled when TMI60 is selected as the count clock. 3. Operation is enabled while the main system clock is selected. 4. Operation is enabled while the subsystem clock is selected. 5. Operation is enabled only when external clock is selected. 6. Maskable interrupt that is not masked User's Manual U15075EJ1V0UM00 281 CHAPTER 15 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed. instruction at the next address is executed. Figure 15-2. Releasing HALT Mode by Interrupt HALT instruction Standby release signal Operation mode If the interrupt is disabled, the Wait HALT mode Wait Oscillation Operation mode Clock Remarks 1. The broken line indicates the case where the interrupt request that has released the standby mode is acknowledged. 2. The wait time is as follows: * When vectored interrupt processing is performed: * When vectored interrupt processing is not performed: (b) Releasing by non-maskable interrupt request The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed. 9 to 10 clocks 1 to 2 clocks 282 User's Manual U15075EJ1V0UM00 CHAPTER 15 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 15-3. Releasing HALT Mode by RESET Input HALT instruction RESET signal Operation mode Reset period Oscillation stops Wait (215/fX: 6.55 ms) HALT mode Oscillation Oscillation stabilization wait status Oscillation Operation mode Clock Remark fX: Main system clock oscillation frequency Table 15-2. Operation After Releasing HALT Mode Releasing Source Maskable interrupt request MKxx 0 0 1 IE 0 1 x x - Operation Executes next address instruction Executes interrupt servicing Retains HALT mode Executes interrupt servicing Reset processing Non-maskable interrupt request RESET input - --- x: don't care User's Manual U15075EJ1V0UM00 283 CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation stabilization time select register (OSTS) elapses, and then an operation mode is set. The operation status in the STOP mode is shown in the following table. Table 15-3. STOP Mode Operating Status STOP Mode Operation Status While The Main System Clock Is Running Item While the subsystem clock is running Main system clock CPU Port (output latch) 16-bit timer 8-bit timer TM50 TM60 Watch timer Watchdog timer Serial interface A/D converter LCD controller/driver External interrupt Oscillation stopped Operation stopped Remains in the state existing before the selection of STOP mode. Operation stopped Operation enabled Note 1 While the subsystem clock is not running Operation enabled Operation enabled Note 2 Note 3 Operation stopped Operation stopped Operation enabled Operation enabled Note 4 Operation stopped Operation enabled Operation enabled Note 3 Operation stopped Note 5 Notes 1. Operation is enabled only when input signal from timer 60 (timer 60 operation is enabled) is selected as the count clock. 2. Operation is enabled when TMI60 is selected as the count clock. 3. Operation is enabled while the subsystem clock is selected. 4. Operation is enabled only when external clock is selected. 5. Maskable interrupt that is not masked 284 User's Manual U15075EJ1V0UM00 CHAPTER 15 STANDBY FUNCTION (2) Releasing STOP mode The STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed. executed. Figure 15-4. Releasing STOP Mode by Interrupt STOP instruction Standby release signal Operation mode Oscillation Oscillation stabilization wait status Oscillation Operation mode Wait (set time by OSTS) If the interrupt is disabled, the instruction at the next address is STOP mode Oscillation stops Clock Remark The broken line indicates the case where the interrupt request that has released the standby mode is acknowledged. User's Manual U15075EJ1V0UM00 285 CHAPTER 15 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 15-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Operation mode Oscillation Reset period Oscillation stabilization wait status Oscillation Operation mode Wait STOP mode Oscillation stops Clock Remark fX: Main system clock oscillation frequency Table 15-4. Operation After Releasing STOP Mode Releasing Source Maskable interrupt request MKxx 0 0 1 IE 0 1 x --- Operation Executes next address instruction Executes interrupt servicing Retains STOP mode Reset processing RESET input - x: don't care 286 User's Manual U15075EJ1V0UM00 CHAPTER 16 RESET FUNCTION The following two operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by watchdog timer runaway time detection External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in Table 16-1. Each pin has a high impedance during reset input or during oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 16-2 to 16-4.) Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. Figure 16-1. Block Diagram of Reset Function RESET Reset controller Reset signal Count clock Watchdog timer Stop Overflow Interrupt function User's Manual U15075EJ1V0UM00 287 CHAPTER 16 RESET FUNCTION Figure 16-2. Reset Timing by RESET Input X1 During normal operation RESET Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal Delay Port pin Delay Hi-Z Figure 16-3. Reset Timing by Overflow in Watchdog Timer X1 During normal operation Overflow in watchdog timer Reset period (oscillation continues) Oscillation stabilization time wait Normal operation (reset processing) Internal reset signal Port pin Hi-Z Figure 16-4. Reset Timing by RESET Input in STOP Mode X1 STOP instruction execution During normal Stop status operation (oscillation stops) RESET Oscillation stabilization time wait Reset period (oscillation stops) Normal operation (reset processing) Internal reset signal Delay Port pin Delay Hi-Z 288 User's Manual U15075EJ1V0UM00 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (1/2) Hardware Program counter (PC) Note 1 Status After Reset The contents of reset vector tables (0000H and 0001H) are set. Undefined 02H Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose register Port (P0 to P3, P5, P7) (Output latch) Port (P8, P9) (Output latch) Note 3 Undefined Undefined 00H 00H FFH FFH 00H 00H 02H 00H 00H 04H 0000H FFFFH 00H Undefined 00H Undefined 00H 00H 00H 00H 00H 00H 00H 00H FFH Note 2 Note 2 Port mode register (PM0 to PM3, PM5, PM7) Port mode register (PM8, PM9) Note 3 Pull-up resistor option register (PU0, PUB2, PUB3, PUB7) Pull-up resistor option register (PUB8 Note 3 , PUB9 Note 3 ) Processor clock control register (PCC) Suboscillation mode register (SCKM) Subclock control register (CSS) Oscillation stabilization time select register (OSTS) 16-bit timer Timer counter (TM90) Compare register (CR90) Control register (TMC90) Capture register (TCP90) 8-bit timer Timer counter (TM50, TM60) Compare register (CR50, CR60, CRH60) Mode control register (TMC50, TMC60) Watch timer Watchdog timer Mode control register (WTM) Clock select register (WDCS) Mode register (WDTM) Serial interface Serial operation mode register (CSIM20) Asynchronous serial interface mode register (ASIM20) Asynchronous serial interface status register (ASIS20) Baud rate generator control register (BRGC20) Transmit shift register (TXS20) Receive buffer register (RXB20) A/D converter A/D conversion result register (ADCR0) Mode register (ADM0) Analog input channel specification register (ADS0) Undefined 0000H 00H 00H Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware remains unchanged after reset. 2. The post-reset values are retained in the standby mode. 3. PD789426, 789436 Subseries only User's Manual U15075EJ1V0UM00 289 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (2/2) Hardware LCD controller/driver Display mode register (LCDM0) Clock control register (LCDC0) Voltage amplification control register (LCDVA0) Interrupt Request flag register (IF0, IF1) Mask flag register (MK0, MK1) External interrupt mode register (INTM0, INTM1) Key return mode register (KRM00) Status After Reset 00H 00H 00H 00H FFH 00H 00H 290 User's Manual U15075EJ1V0UM00 CHAPTER 17 PD78F9436, 78F9456 The PD78F9436 and 78F9456 are available as the flash memory versions of the PD789426, 789436, 789446, and 789456 Subseries. The PD78F9436 is a version with the internal ROM of the PD789426 and 789436 Subseries replaced with flash memory and the PD78F9456 is a version with the internal ROM of the PD789446 and 789456 Subseries replaced with flash memory. The differences between the PD78F9436, 78F9456 and the mask ROM versions are shown in Table 17-1. Table 17-1. Differences Between PD78F9436, 78F9456 and Mask ROM Versions Part Number Item Flash Memory Version Mask ROM Version PD78F9436 PD78F9456 PD789425, 789435 12 KB PD789426, 789436 16 KB PD789445, 789455 12 KB PD789446, 789456 16 KB Internal memory ROM High-speed RAM 12 KB 512 bytes 16 KB LCD display RAM 5 bytes IC pin VPP pin Electrical specifications Not provided Provided 15 bytes 5 bytes Provided Not provided 15 bytes Varies depending on flash memory or mask ROM versions. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. User's Manual U15075EJ1V0UM00 291 CHAPTER 17 PD78F9436, 78F9456 17.1 Flash Memory Programming The on-chip program memory in the PD78F9436 and 78F9456 is a flash memory. The flash memory can be written with the PD78F9436 and 78F9456 mounted on the target system (on-board). Connect the dedicated flash writer (Flashpro III (part no. FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory. Remark FL-PR3 is made by Naito Densei Machida Mfg Co., Ltd. 17.1.1 Selecting communication mode The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 17-2. To select a communication mode, the format shown in Figure 17-1 is used. Each communication mode is selected by the number of VPP pulses shown in Table 17-2. Table 17-2. Communication Mode Communication Mode 3-wire serial I/O Pins Used SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25 TxD20/SO20/P24 RxD20/SI20/P25 0 Number of VPP Pulses UART 8 Caution Be sure to select a communication mode depending on the number of VPP pulses shown in Table 17-2. Figure 17-1. Communication Mode Selection Format 10 V VPP VDD VSS 1 2 n VDD RESET VSS 292 User's Manual U15075EJ1V0UM00 CHAPTER 17 PD78F9436, 78F9456 17.1.2 Function of flash memory programming By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 17-3 shows the major functions of flash memory programming. Table 17-3. Functions of Flash Memory Programming Function Batch erase Batch blank check Data write Batch verify Erases all contents of memory Checks erased state of entire memory Write to flash memory based on write start address and number of data written (number of bytes) Compares all contents of memory with input data Description 17.1.3 Flashpro III connection example How the Flashpro III is connected to the PD78F9436 or 78F9456 differs depending on the communication mode (3-wire serial I/O or UART). Figures 17-2 and 17-3 show the connection in the respective modes. Figure 17-2. Flashpro III Connection Example in 3-Wire Serial I/O Mode Flashpro III VPPnNote VDD RESET CLK SCK SO SI GND PD78F9436, 78F9456 VPP VDD, AVDD RESET X1 SCK20 SI20 SO20 VSS, AVSS Note n = 1, 2 User's Manual U15075EJ1V0UM00 293 CHAPTER 17 PD78F9436, 78F9456 Figure 17-3. Flashpro III Connection Example in UART Mode Flashpro III VPPnNote VDD RESET CLK SO SI GND PD78F9436, 78F9456 VPP VDD, AVDD RESET X1 RxD20 TxD20 VSS, AVSS Note n = 1, 2 294 User's Manual U15075EJ1V0UM00 CHAPTER 17 PD78F9436, 78F9456 17.1.4 Example of settings for Flashpro III (PG-FP3) Make the following settings when writing to flash memory using Flashpro III (PG-FP3). <1> Load the parameter file. <2> Select the serial mode and serial clock using the type command. <3> An example of settings for the PG-FP3 is shown below. Table 17-4. Example of Settings for PG-FP3 Communication Mode 3-wire serial I/O COMM PORT CPU CLK Example of Settings for PG-FP3 SIO-ch0 On Target Board In Flashpro On Target Board SIO CLK In Flashpro SIO CLK UART COMM PORT CPU CLK On Target Board UART BPS 4.1943 MHz 1.0 MHz 4.0 MHz 1.0 MHz UART-ch0 On Target Board 4.1943 MHz 9600 bps Note 2 Number of VPP Pulses 0 Note 1 8 Notes 1. The number of VPP pulses supplied from Flashpro III when serial communication is initialized. The pins to be used for communication are determined according to the number of these pulses. 2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. Remark COMM PORT: Selection of serial port SIO CLK: CPU CLK: Selection of serial clock frequency Selection of source of CPU clock to be input User's Manual U15075EJ1V0UM00 295 [MEMO] 296 User's Manual U15075EJ1V0UM00 CHAPTER 18 MASK OPTIONS Table 18-1. Selection of Mask Option for Pins Pin P50 to P53 Mask Option Whether a pull-up resistor is to be incorporated can be specified in 1-bit units. For P50 to P53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. The mask option is selectable in 1-bit units. Caution Flash memory versions do not have a mask option-based on-chip pull-up resistor function. User's Manual U15075EJ1V0UM00 297 [MEMO] 298 User's Manual U15075EJ1V0UM00 CHAPTER 19 INSTRUCTION SET This chapter lists the instruction set of the PD789426, 789436, 789446, and 789456 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). and are described as they are. Each symbol has the following meaning. * #: * !: Immediate data specification Absolute address specification * $: * [ ]: Relative address specification Indirect address specification When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for description. Table 19-1. Operand Identifiers and Description Methods Identifier r rp sfr saddr saddrp addr16 addr5 word byte bit Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbol FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even addresses only) 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) 0040H to 007FH Immediate data or labels (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label Remark See Table 3-4 Special Function Register List for symbols of special function registers. User's Manual U15075EJ1V0UM00 299 CHAPTER 19 INSTRUCTION SET 19.1.2 Description of "Operation" column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): XH, XL: : : V: -: addr16: jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non-maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data 16-bit immediate data or label Signed 8-bit data (displacement value) 19.1.3 Description of "Flag" column (Blank): 0: 1: x: R: Unchanged Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored 300 User's Manual U15075EJ1V0UM00 CHAPTER 19 INSTRUCTION SET 19.2 Operation List Mnemonic Operands Byte Clock Operation Flag Z AC CY MOV r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL+byte] [HL+byte], A XCH A, X A, r A, saddr A, sfr A, [DE] A, [HL] A, [HL+byte] Note 2 Note 1 3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A AX Ar A (saddr) A sfr A (DE) A (HL) A (HL + byte) x x x x x x Note 1 Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U15075EJ1V0UM00 301 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX Note 3 2 2 1 1 1 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 6 6 8 4 4 8 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Note XCHW ADD AX, rp A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] Note ADDC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] SUB A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 302 User's Manual U15075EJ1V0UM00 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY SUBC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A V byte (saddr) (saddr) V byte AAVr A A V (saddr) A A V (addr16) A A V (HL) A A V (HL + byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x AND A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] OR A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] XOR A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U15075EJ1V0UM00 303 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY CMP A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL+byte] 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1 3 3 2 3 2 3 3 2 3 2 1 1 1 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2 6 6 4 6 10 6 6 4 6 10 2 2 2 A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL + byte) AX, CY AX + word AX, CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr+1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am-1 Am) x 1 (CY, A0 A7, Am+1 Am) x 1 (CY A0, A7 CY, Am-1 Am) x 1 (CY A7, A0 CY, Am+1 Am) x 1 (saddr.bit) 1 sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x ADDW SUBW CMPW INC AX, #word AX, #word AX, #word r saddr DEC r saddr INCW DECW ROR ROL RORC ROLC SET1 rp rp A, 1 A, 1 A, 1 A, 1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x x x x x x CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit x x x SET1 CLR1 NOT1 CY CY CY 1 0 x Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 304 User's Manual U15075EJ1V0UM00 CHAPTER 19 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 4 + jdisp8 if PSW.bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 No Operation IE 1 (Enable interrupt) IE 0 (Disable interrupt) Set HALT mode Set STOP mode R R R R R R CALLT [addr5] 1 8 RET RETI 1 1 6 8 PUSH PSW rp 1 1 1 1 2 2 3 2 1 2 2 2 2 4 4 3 4 4 4 3 4 2 2 3 2 4 4 6 8 6 6 6 6 6 6 6 6 10 10 8 10 10 10 8 10 6 6 8 POP PSW rp MOVW SP, AX AX, SP BR !addr16 $addr16 AX BC BNC BZ BNZ BT $saddr16 $saddr16 $saddr16 $saddr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 BF saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 DBNZ B, $addr16 C, $addr16 saddr, $addr16 NOP EI DI HALT STOP 1 3 3 1 1 2 6 6 2 2 Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U15075EJ1V0UM00 305 CHAPTER 19 INSTRUCTION SET 19.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand 1st Operand A #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte] $addr16 1 None ADD ADDC SUB SUBC AND OR XOR CMP MOVNote MOV XCHNote XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV INC DEC DBNZ B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV DBNZ INC DEC !addr16 PSW MOV MOV MOV PUSH POP [DE] [HL] [HL+byte] MOV MOV MOV Note Except r = A. 306 User's Manual U15075EJ1V0UM00 CHAPTER 19 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand 1st Operand AX ADDW SUBW CMPW MOVW MOVW Note #word AX rp Note saddrp SP None MOVW XCHW MOVW MOVW rp INCW DECW PUSH POP saddrp SP MOVW MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand 1st Operand A.bit BT BF BT BF BT BF BT BF SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 $addr16 None sfr.bit saddr.bit PSW.bit [HL].bit CY User's Manual U15075EJ1V0UM00 307 CHAPTER 19 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ DBNZ AX !addr16 [addr5] $addr16 Compound Instructions (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP 308 User's Manual U15075EJ1V0UM00 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the PD789426, 789436, 789446, and 789456 Subseries. Figure A-1 shows development tools. * Support to PC98-NX Series Unless specified otherwise, the products supported by IBM PC/ATTM compatibles can be used in PC98-NX Series. When using the PC98-NX Series, refer to the explanation of IBM PC/AT compatibles. * Windows Unless specified otherwise, "Windows" indicates the following operating systems. * Windows 3.1 * Windows 95 * Windows NTTM Ver.4.0 User's Manual U15075EJ1V0UM00 309 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Language processing software * Assembler package * C compiler package * System simulator * Device file * C compiler source file * Integrated debugger Embedded software * OS Host machine (PC or EWS) Interface adapter Flash memory writing tools Flash programmer In-circuit emulator Emulation board Power supply unit Flash memory writing adapter Flash memory Emulation probe Conversion adapter Target system 310 User's Manual U15075EJ1V0UM00 APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K0S Assembler package Program that converts program written in mnemonic into object codes that can be executed by microcontroller. In addition, automatic functions to generate symbol table and optimize branch instructions are also provided. Used in combination with optional device file (DF789456). Note File containing the information inherent to the device. Used in combination with optional RA78K0S, CC78K0S, and SM78K0S. Part number: SxxxxDF789456 CC78K0S-L C compiler source file Source file of functions for generating object library included in C compiler package. Necessary for changing object library included in C compiler package according to customer's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L Note DF789456 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S. Remark xxxx in the part number differs depending on the host machines and operating systems to be used. SxxxxRA78K0S SxxxxCC78K0S SxxxxDF789456 SxxxxCC78K0S-L xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13 NEWS (RISC) TM Host Machine PC-9800 series IBM PC/AT compatibles OS Japanese Windows Japanese Windows English Windows Note Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Note HP9000 series 700 SPARCstation TM TM HP-UX (Rel. 10.10) SunOS (Rel. 4.1.1), Solaris (Rel. 2.5.1) NEWS-OS (Rel. 6.1) TM TM TM TM DAT (DDS) 3.5" 2HC FD 1/4" CGMT 3.5" 2HC FD Note Also operates under the DOS environment. User's Manual U15075EJ1V0UM00 311 APPENDIX A DEVELOPMENT TOOLS A.2 Flash Memory Writing Tools Flashpro III (Part No. FL-PR3, PG-FP3) Flash programmer FA-64GK Flash memory writing adapter Dedicated flash programmer for microcomputers incorporating flash memory Adapter for writing to flash memory and connected to Flashpro III. * FA-64GK: for 64-pin plastic TQFP (fine pitch) (GK-9ET type) Remark The FL-PR3 and FA-64GK are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44822-3813). 312 User's Manual U15075EJ1V0UM00 APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware IE-78K0S-NS In-circuit emulator In-circuit emulator for debugging hardware and software of application system using 78K/0S Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. Adapter for supplying power from AC 100 to 240 V outlet. IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-789456-NS-EM1 Emulation board NP-64GK Emulation probe TGK-064SBW, TGK-064SBP Conversion adapter Adapter necessary when using PC-9800 series PC (except notebook type) as host machine of IE-78K0S-NS (C bus supported) PC card and interface cable necessary when using notebook PC as host machine of IE-78K0SNS (PCMCIA socket supported) Interface adapter necessary when using IBM PC/AT compatible as host machine of IE-78K0SNS (ISA bus supported) Adapter necessary when using personal computer incorporating PCI bus as host machine of IE78K0S-NS Board for emulating the peripheral hardware inherent to the device. Used in combination with incircuit emulator. Probe to connect the in-circuit emulator and target system. Used in combination with the TGK-064SBW and TGK-064SBP. Conversion socket to connect the NP-64GK and a target system board on which a 64-pin plastic TQFP (fine pitch) (GK-9ET type) can be mounted Remarks 1. The NP-64GK is a product made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). 2. The TGK-064SBW and TGK-064SBP are products made by TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) User's Manual U15075EJ1V0UM00 313 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software ID78K0S-NS Integrated debugger (Supports in-circuit emulator IE-78K0S-NS) Control program for debugging 78K/0S Series. This program provides a graphical use interface. It runs on Windows for personal computer TM users and on OSF/Motif for engineering work station users, and has visual designs and operationability that comply with these operating systems. In addition, it has a powerful debug function that supports C language. Therefore, trace results can be displayed at a C language level by the window integration function that links source program, disassembled display, and memory display, to the trace result. This software also allows users to add other function extension modules such as task debugger and system performance analyzer to improve the debug efficiency for programs using a real-time operating system. Used in combination with optional device file (DF789456). Part number: SxxxxID78K0S-NS Remark xxxx in the part number differs depending on the host machines and operating systems to be used. SxxxxID78K0S-NS xxxx AA13 AB13 BB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Japanese Windows Japanese Windows English Windows Note Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Note Note Also operates under the DOS environment. SM78K0S System simulator Debugs program at C source level or assembler level while simulating operation of target system on host machine. SM78K0S runs under Windows. By using SM78K0S, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. This enhances development efficiency and improves software quality. Used in combination with optional device file (DF789456). Part number: SxxxxSM78K0S DF789456 Device file Note File containing the information inherent to the device. Used in combination with the optional RA78K0S, CC78K0S, and SM78K0S. Part number: SxxxxDF789456 Note DF789456 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S. Remark xxxx in the part number differs depending on the host machines and operating systems to be used. SxxxxSM78K0S xxxx AA13 AB13 BB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Japanese Windows Japanese Windows English Windows Note Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Note Note Also operates under the DOS environment. 314 User's Manual U15075EJ1V0UM00 APPENDIX B EMBEDDED SOFTWARE The following embedded software is provided to perform the program development and maintenance of the PD789426, 789436, 789446, and 789456 Subseries effectively. MX78K0S OS Subset OS conformed to ITRON. Includes the nucleus of the MX78K0S. Task control, event control, and time control are performed. In the task control, task execution sequences are controlled to switch the task to be executed next. Remark xxxx in the part number differs depending on the host machines and operating systems to be used. SxxxxMX78K0S xxxx AA13 AB13 BB13 Host Machine PC-9800 series IBM PC/AT compatibles OS Japanese Windows Japanese Windows English Windows Note Supply Media 3.5" 2HD FD 3.5" 2HC FD Note Note Note Also operates under the DOS environment. User's Manual U15075EJ1V0UM00 315 [MEMO] 316 User's Manual U15075EJ1V0UM00 APPENDIX C REGISTER INDEX C.1 Register Index (Alphabetic Order of Register Name) [A] Analog input channel specification register 0 (ADS0).................................................................................. 187, 201 A/D conversion result register 0 (ADCR0) ................................................................................................... 184, 198 A/D converter mode register 0 (ADM0)........................................................................................................ 186, 200 Asynchronous serial interface mode register 20 (ASIM20).......................................................... 216, 223, 226, 238 Asynchronous serial interface status register 20 (ASIS20).......................................................................... 218, 227 [B] Baud rate generator control register 20 (BRGC20) ............................................................................. 219, 228, 239 Buzzer output control register 90 (BZC90) .......................................................................................................... 121 [C] Carrier generator output control register 60 (TCA60) .......................................................................................... 142 [E] 8-bit compare register 50 (CR50) ........................................................................................................................ 135 8-bit compare register 60 (CR60) ........................................................................................................................ 135 8-bit compare register H60 (CRH60) ................................................................................................................... 135 8-bit timer counter 50 (TM50) .............................................................................................................................. 136 8-bit timer counter 60 (TM60) .............................................................................................................................. 136 8-bit timer mode control register 50 (TMC50) .............................................................................................. 138, 139 8-bit timer mode control register 60 (TMC60) .............................................................................................. 140, 141 External interrupt mode register 0 (INTM0) ......................................................................................................... 269 External interrupt mode register 1 (INTM1) ................................................................................................. 269, 270 [I] Interrupt mask flag register 0, 1 (MK0, MK1) ....................................................................................................... 268 Interrupt request flag register 0, 1 (IF0, IF1) ........................................................................................................ 267 [K] Key return mode register 00 (KRM00) ................................................................................................................. 271 [L] LCD clock control register 0 (LCDC0).................................................................................................................. 251 LCD display mode register 0 (LCDM0) ........................................................................................................ 249, 250 LCD voltage amplification control register 0 (LCDVA0) ....................................................................................... 252 [O] Oscillation stabilization time select register (OSTS) ............................................................................................ 280 [P] Port 0 (P0).............................................................................................................................................................. 81 User's Manual U15075EJ1V0UM00 317 APPENDIX C REGISTER INDEX Port 1 (P1).............................................................................................................................................................. 82 Port 2 (P2).............................................................................................................................................................. 83 Port 3 (P3).............................................................................................................................................................. 89 Port 5 (P5).............................................................................................................................................................. 91 Port 6 (P6).............................................................................................................................................................. 92 Port 7 (P7).............................................................................................................................................................. 93 Port 8 (P8).............................................................................................................................................................. 94 Port 9 (P9).............................................................................................................................................................. 95 Port mode register 0 (PM0).............................................................................................................................. 96, 97 Port mode register 1 (PM1).............................................................................................................................. 96, 97 Port mode register 2 (PM2)...................................................................................................................... 96, 97, 122 Port mode register 3 (PM3)...................................................................................................................... 96, 97, 142 Port mode register 5 (PM5).............................................................................................................................. 96, 97 Port mode register 7 (PM7).............................................................................................................................. 96, 97 Port mode register 8 (PM8).............................................................................................................................. 96, 97 Port mode register 9 (PM9).............................................................................................................................. 96, 97 Processor clock control register (PCC) ................................................................................................................ 105 Pull-up resistor option register 0 (PU0) .................................................................................................................. 98 Pull-up resistor option register B2 (PUB2) ............................................................................................................. 99 Pull-up resistor option register B3 (PUB3) ............................................................................................................. 99 Pull-up resistor option register B7 (PUB7) ........................................................................................................... 100 Pull-up resistor option register B8 (PUB8) ........................................................................................................... 100 Pull-up resistor option register B9 (PUB9) ........................................................................................................... 101 [R] Receive buffer register 20 (RXB20) ..................................................................................................................... 214 [S] Serial operation mode register 20 (CSIM20)................................................................................ 215, 222, 225, 237 Subclock control register (CSS) ........................................................................................................................... 107 Suboscillation mode register (SCKM) .................................................................................................................. 106 16-bit capture register 90 (TCP90)....................................................................................................................... 118 16-bit compare register 90 (CR90)....................................................................................................................... 118 16-bit timer counter 90 (TM90)............................................................................................................................. 118 16-bit timer mode control register 90 (TMC90) ............................................................................................ 119, 120 [T] Transmit shift register 20 (TXS20) ....................................................................................................................... 214 [W] Watch timer mode control register (WTM) ........................................................................................................... 173 Watchdog timer clock select register (WDCS) ..................................................................................................... 179 Watchdog timer mode register (WDTM) .............................................................................................................. 180 318 User's Manual U15075EJ1V0UM00 APPENDIX C REGISTER INDEX C.2 Register Index (Alphabetic Order of Register Symbol) [A] ADCR0: ADM0: ADS0: ASIS20: [B] BRGC20: Baud rate generator control register 20 .............................................................................. 219, 228, 239 BZC90: [C] CR50: CR60: CR90: CRH60: CSS: [I] IF0: IF1: INTM0: INTM1: [K] KRM00: [L] LCDC0: LCDM0: LCD clock control register 0................................................................................................................ 251 LCD display mode register 0....................................................................................................... 249, 280 Key return mode register 00 ............................................................................................................... 271 Interrupt request flag register 0........................................................................................................... 267 Interrupt request flag register 1........................................................................................................... 267 External interrupt mode register 0....................................................................................................... 269 External interrupt mode register 1............................................................................................... 269, 270 8-bit compare register 50 .................................................................................................................... 135 8-bit compare register 60 .................................................................................................................... 135 16-bit compare register 90 .................................................................................................................. 118 8-bit compare register H60 ................................................................................................................. 135 Subclock control register..................................................................................................................... 107 Buzzer output control register 90 ........................................................................................................ 121 A/D conversion result register 0.................................................................................................. 184, 198 A/D converter mode register 0 .................................................................................................... 186, 200 Analog input channel specification register 0.............................................................................. 187, 201 Asynchronous serial interface status register 20 ........................................................................ 218, 227 ASIM20: Asynchronous serial interface mode register 20......................................................... 216, 223, 226, 238 CSIM20: Serial operation mode register 20............................................................................... 215, 222, 225, 237 LCDVA0: LCD voltage amplification control register 0 ....................................................................................... 252 [M] MK0: MK1: [O] OSTS: [P] P0: P1: P2: P3: Port 0 .................................................................................................................................................... 81 Port 1 .................................................................................................................................................... 82 Port 2 .................................................................................................................................................... 83 Port 3 .................................................................................................................................................... 89 User's Manual U15075EJ1V0UM00 Interrupt mask flag register 0 .............................................................................................................. 268 Interrupt mask flag register 1 .............................................................................................................. 268 Oscillation stabilization time select register ........................................................................................ 280 319 APPENDIX C REGISTER INDEX P5: P6: P7: P8: P9: PCC: PM0: PM1: PM2: PM3: PM5: PM7: PM8: PM9: PU0: PUB2: PUB3: PUB7: PUB8: PUB9: [R] RXB20: [S] SCKM: [T] TCA60: TCP90: TM50: TM60: TM90: TMC50: TMC60: TMC90: TXS20: [W] WDCS: WDTM: WTM: Port 5..................................................................................................................................................... 91 Port 6..................................................................................................................................................... 92 Port 7..................................................................................................................................................... 93 Port 8..................................................................................................................................................... 94 Port 9..................................................................................................................................................... 95 Processor clock control register .......................................................................................................... 105 Port mode register 0........................................................................................................................ 96, 97 Port mode register 1........................................................................................................................ 96, 97 Port mode register 2................................................................................................................ 96, 97, 122 Port mode register 3................................................................................................................ 96, 97, 142 Port mode register 5........................................................................................................................ 96, 97 Port mode register 7........................................................................................................................ 96, 97 Port mode register 8........................................................................................................................ 96, 97 Port mode register 9........................................................................................................................ 96, 97 Pull-up resistor option register 0 ........................................................................................................... 98 Pull-up resistor option register B2 ......................................................................................................... 99 Pull-up resistor option register B3 ......................................................................................................... 99 Pull-up resistor option register B7 ....................................................................................................... 100 Pull-up resistor option register B8 ....................................................................................................... 100 Pull-up resistor option register B9 ....................................................................................................... 101 Receive buffer register 20 ................................................................................................................... 214 Suboscillation mode register ............................................................................................................... 106 Carrier generator output control register 60 ........................................................................................ 142 16-bit capture register 90 .................................................................................................................... 118 8-bit timer counter 50 .......................................................................................................................... 136 8-bit timer counter 60 .......................................................................................................................... 136 16-bit timer counter 90 ........................................................................................................................ 118 8-bit timer mode control register 50 ............................................................................................ 138, 139 8-bit timer mode control register 60 ............................................................................................ 140, 141 16-bit timer mode control register 90 .......................................................................................... 119, 120 Transmit shift register 20..................................................................................................................... 214 Watchdog timer clock select register .................................................................................................. 179 Watchdog timer mode register ............................................................................................................ 180 Watch timer mode control register ...................................................................................................... 173 320 User's Manual U15075EJ1V0UM00 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6462-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: 044-435-9608 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 00.6 Excellent Good Acceptable Poor |
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